fpga4fun.com

hello everybody

the serial interface project implements the UART , and it contains only 2 files one for transmitter and the other for reciever
but the UART doesn't only have transmitter and reciever it also have a main part which is a small memory uses FIFO algorithm , this memory is used to make flow control because CPU and FPGA are very faster than the serial UART transmission and recieving
i think this part must be implemented too

so i can't fogure out are these 2 files enough to make full communication between PC and FPGA without errors?

THANKS

FIFOs are not always required since RS232 is so slow. For example in an FPGA you can usually have a state machine that waits for data coming and process it right away.

But FIFOs can be useful in other cases. I'll leave that to you.