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I'm trying to design a 64 to 1 multiplexer, and im using tri-state buffers, however, it seems to be really big, and uses alot of space to where it seems it wouldnt be efficent. Is there an eaiser way to design such a large multiplexer?

You shouldn't need tri-state buffers if your multiplexer is all inside the FPGA. Also new FPGA families don't support natively internal tri-state buffes (instead they emulate them with non-tristate muxes).