VGA Signal in VHDL, Overlapping problem

FPGA projects on this site, or abroad

VGA Signal in VHDL, Overlapping problem

Postby alveru » Mon Sep 05, 2005 11:01 am

Help :cry: !!!!

Hi everybody, I was trying to generate the video signal with a Cyclone board from Altera using a crystal with 50 MHz.

When i download the code into the FPGA I have the problem that I cannot control every single pixel nor line. When I try to draw one line white and one line black; and so on; there seems to be an overlapping problem between vertical lines, although the timing I've used is correct. But not in every single line; that occurs perhaps every 50 or 60 lines, the lines appear mixed by 3 or 4 lines with some kind of blur, then the next 50 lines are ok again and so on, this is quite weird. :shock:

if anyone know what's the problem, I'd appreciate some help. I attach the code below, very simple.

:cry:


-- new clock frequency, 50MHz /2 = 25 MHz

new_clock <= not new_clock when rising_edge(clock) else
unaffected;

-- this process generates exacly 31.8 us for the complete H signal

Process(new_clock, reset)
Begin
if reset = '0' then
Counter_HS <= (others => '0');
Counter_VS <= (others => '0');
elsif rising_edge(new_clock) then
if Counter_HS = 795 then
Counter_HS <= (others => '0');
Counter_VS <= Counter_VS + 1;
else
Counter_HS <= Counter_HS + 1; end if;
end if;
End Process;

-- This process generates the 3.76 us for syncronize the H signal

Process(new_clock, reset)
Begin
if reset = '0' then
vga_HS <= '1';
elsif rising_edge(new_clock) then
if Counter_HS < 94 then
vga_HS <= '0';
else
vga_HS <= '1';
end if;
end if;
End process;

-- This process generates the 63.6 ms for syncronize the V signal

Process(new_clock, clock, reset)
Begin
if reset = '0' then
vga_VS <= '1';
elsif rising_edge(new_clock) then
if Counter_VS < 1 then
vga_VS <= '0';
else
vga_VS <= '1';
end if;
end if;
End process;


-----------------------------------------------------------------------
-- Just paint one line color, and line black and so on.

Process(new_clock, clock, reset)
Begin
if reset = '0' then

elsif rising_edge(new_clock) then

if Counter_HS > 142 and Counter_HS < 780 and
Counter_VS > 5 and Counter_VS < 470 then
RGB<= Counter_HS(0)&"00";
else
RGB <= "000";
end if;

end if;
End process;
alveru
 
Posts: 5
Joined: Tue Jun 28, 2005 12:36 am

problem solved using test and error.

Postby alveru » Mon Sep 12, 2005 8:49 am

I have changed the fixed values from very low to very high values and the problem seems to be gone.

it looks like the configuration for the horizontal and vertical frequencies cannot be calculated, you have to get them by testing only.

if someone is interested, i use for the horizontal counter 799 and for vertical 525, now i can control every single pixel on the screen using a 50Mhz clock, now the values are almost exact to the VGA official specification.

:shock:
alveru
 
Posts: 5
Joined: Tue Jun 28, 2005 12:36 am


Return to General projects