fpga4fun.com

Hi: First, thank you for a great site - I needed to find a place like this. Sometimes all the books in the world can't replace a few words from a live human!

I emailed Jean on this subject. My question was how could I get this serial uart transmitter to simulate. As per Jean's suggestion, I added reset to the sensitivity lists for all the reg's, and voila - it now simulates fine.

Is there a way to upload a screenshot of my simulation to this bbs? It doesn't appear that one can, but perhaps someone here can enlighten me.

So thanks again, and I'll keep checking in.

Happy that this solved the problem.
You can send me the files (the modified HDL files and the screenshots), I'll put a link for them.

I don't know verilog, but I know VHDL a little. If anyone have VHDL code for Ehernet receiver/transiever (or can translate it) please mail me. ug_1982_10_03@yahoo.com . Thanks!

my question is: how can I use this code ? if I run it from ISE, so which process I have to do ?

Hi there,

Are the 'modified HDL files and the screenshots' available somewhere ? Or these are the files from the current serial communication example project ? If not, I didn't found them.

Thanks