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Hi guys,

I'm trying to write a BCD module which takes 5bit input and 8bit output. But I can't quiet get it to work. It uses the double dabble algorithm, here's what I have so far:

Code: Select all

module bcd(binary, bcd);
   input [4:0]binary;
   output [7:0]bcd;
   
   wire [12:0]w0,w1,w2,w3;
   assign w0 = binary<<3;
   add3 (.in(w0), .out(w1));
   add3 (.in(w1<<1), .out(w2));
   add3 (.in(w2<<1), .out(w3));
   assign bcd = w3[12:5];
endmodule


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module add3( in, out);
   input [12:0]in;
   output [12:0]out;
   reg [12:0]_in;
   
   always@(in)
   begin
      _in = in;
      if(in[12:9]>4) _in[12:9] = _in[12:9] + 3;
      if(in[8:5]>4) _in = _in + 3;
   end
   
   assign out = _in;
endmodule

It seems like the binary goes through unchanged! Which I assume means +3 never happens... But why?! Any ideas?

Update:
I removed the final add3 now it works perfectly.
Here's the final code in working order.

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module bcd(in, out);
    input [4:0]in;
    output [7:0]out;
   
    wire [12:0]w0,w1,w2,w3;
    assign w0 = in;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    assign w3 = w2 << 1;
    assign out[7:0] = w3[12:5];
endmodule

Code: Select all

module add3(in, out);
    input [12:0]in;
    output [12:0]out;
    reg [12:0]out;
   
    always@(*)
    begin
        out = in;
        if(in[12:9]>4) out[12:9] = in[12:9] + 3;
        if(in[8:5]>4) out[8:5] = in[8:5] + 3;
    end
endmodule

This is working a great deal better. Based on advice form here.