fpga4fun.com

Hi all, I need your help.

i have study RS232 Receiver on the site : http://www.fpga4fun.com/SerialInterface4.html

there are some sentence is elusive. Is some one could give a explain?

reg [1:0] RxD_cnt;
reg RxD_bit;

always @(posedge clk)
if(Baud8Tick)
begin
if(RxD_sync[1] && RxD_cnt!=2'b11) RxD_cnt <= RxD_cnt + 1;
else
if(~RxD_sync[1] && RxD_cnt!=2'b00) RxD_cnt <= RxD_cnt - 1;

if(RxD_cnt==2'b00) RxD_bit <= 0;
else
if(RxD_cnt==2'b11) RxD_bit <= 1;
end

Hi,

It is filtering the signal on RxD_sync[1] to give RxD_bit, which is delayed a small bit but free of any transient glitches.

I achieves this by forcing RxD_sync[1] to be stable for at least three Baud8Ticks before RxD_bit will flip to match RxD_sync[1]'s state.

It might be for noise immunity or more likely to ensure that the signal is being sampled well away from the rising/falling edge the pulse.

Mike