fpga4fun.com

Hi!

I was wondering if the clock output that goes to the FPGA (for FIFO/SRAM sync) was inverted with respect to the CLOCK input that goes to the 8 bit ADC (that you use in your projects).

I'm asking this because I would like to modify your Flashy project and do data acquisition using a more precise (not necessarily faster) ADC.

For example, ADC12L080 has a clock input on which the analog signal is sampled. The inverted clock signal is sent to two memory latches that read the ADC's digital outputs. If I were to replace the memory latches with the inputs of Pluto3, then according to the datasheet (http://www.national.com/profile/snip.cgi/openDS=ADC12L080), the inverted clock signal should be tied to the FPGA clock pin.

Did I miss something?

Thank you.

Do you own a KNJN FPGA board? if so, take a look at the FlashyMini project to see how the clock is handled.

I have a Pluto 3, but no Flashy.

As much as I understood, the ADC clock (on the Flashy) is the same clock line that goes to the FPGA's clock line.

Yes.