fpga4fun.com

I am an optical engineer and I have little experience in logic and design. However I want to learn how to clock the focal plane arrays that I work with. These FPAs are imaging chips, the readouts are cmos. Before I dive in with some hardware and tutorials I want to make sure I go down the most productive path for this purpose. There are three questions I need to answer. I was hoping I could get some feedback from folks with experience across the programmable logic spectrum.

From my research it seems that FPGAs (vs CPLDs) are better at calculations you might desire in image processing, but the extra complexity might create some internal latencies that would adversely effect clocking performance. Which device type would be generally more optimized to precise, low jitter high speed clocking, a CPLD or an FPGA? Perhaps neither and I should be looking at clocking specific devices with pll's like the lattice ispclock or the cypress roboclocks?

As far as programming the device, I get the impression that VHDL is more timing oriented then verilog. Is that a fair assessment?

Finally, which software package is easier for clock generation? It would be fantastic if I could just define the timing pattern I expect to come out by drawing in a gui rather then doing any programming at all.

Thanks! Please feel free to tell me if I am splitting hairs and either solution works equally.

What kind of clock requirements do you have?
FPGAs might be good at image processing, but not particularly good as clock generators. If you need low-jitter clocks, specialized chips are better.

Neither VHDL nor Verilog are timing oriented. You can describe signals using timing delays with them, but this won't be useful for you since only the functional part of VHDL or Verilog gets into an FPGA. The timing info is used only during simulation.

If you need timing patterns, FPGAs or CPLDs could produce that. FPGAs have internal RAMs, so that could be an easy way to create arbitrary signals.

I don't have any specific requirements yet. I want to get to a place where someone could hand me a new imager chip and I could synthesize the clocks it requires and plug its analog outputs into some frame grabber board. The A/D resolution and convert rate of that frame grabber would also depend on that fpa chip, tbd.

Before that I reckon I have to do lots of tutorials where I make LEDs flash. I'm just wondering if there are any rules of thumb that might indicate some hardware over another. LED blinking might not matter, but the fpa clocking might and I'd like to have been working on the right one all along.

For example on page 497 of Skahill's VHDL manual he says cplds "have more deterministic timing" which leads me to believe I might have less problems implementing reliable timing patterns with them vs. fpgas. Maybe the difference is insignificant though and FPGAs are better for some other reasons. Just like to get your thoughts on that. IF your opinion is "it doesn't really matter" I'm open to that too.

Since CPLDs are composed of a smaller number of logic-elements than FPGAs, it is quite possible that they have more deterministic timing.
Now I've never used either of these devices to create complex or low-jitter clocks, so I can't comment on how good or bad they are.

CPLDs are designed so that all signals have a fairly equal propagation delay so they have a more predictable timing than FPGAs.

You could also buffer a FPGA with a CPLD or other circuit if the clock signals needs extremely low jitter.

If all the signals are latched internally close to the output pin of the FPGA then the jitter will be low. If the output signal is the result of of several signals from different areas of the chip and is routed directly to an output pin then you could have significant jitter.