I am an optical engineer and I have little experience in logic and design. However I want to learn how to clock the focal plane arrays that I work with. These FPAs are imaging chips, the readouts are cmos. Before I dive in with some hardware and tutorials I want to make sure I go down the most productive path for this purpose. There are three questions I need to answer. I was hoping I could get some feedback from folks with experience across the programmable logic spectrum.
From my research it seems that FPGAs (vs CPLDs) are better at calculations you might desire in image processing, but the extra complexity might create some internal latencies that would adversely effect clocking performance. Which device type would be generally more optimized to precise, low jitter high speed clocking, a CPLD or an FPGA? Perhaps neither and I should be looking at clocking specific devices with pll's like the lattice ispclock or the cypress roboclocks?
As far as programming the device, I get the impression that VHDL is more timing oriented then verilog. Is that a fair assessment?
Finally, which software package is easier for clock generation? It would be fantastic if I could just define the timing pattern I expect to come out by drawing in a gui rather then doing any programming at all.
Thanks! Please feel free to tell me if I am splitting hairs and either solution works equally.