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Create a pulse triggerd by one(slow) clock for a period of 1 clock cycle of another(faster) clock.

for a clearer view :

http://tinypic.com/view.php?pic=2q384xz&s=5.

i have done this by doing the following code:

{PS2_CLK : in std_logic;
PS2_DATA: in std_logic;

signal pulse : std_logic:='0';}

begin
pulsey:process(PS2_CLK,CLK) --LINE 37
begin

if falling_edge(PS2_CLK) then

pulse<='1';

end if;

if rising_edge(CLK) then

if pulse ='1' then


pulse<='0';


end if;

end if;


end process;


but this synthesis error comes up:

line 37: Signal pulse cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

HELPP!!!

hi ryan,

a hardware description in which a signal depends on two clocks is not synthesisable. Just handle PS2_CLK as a signal and do an edge detection on it.

thx man it worked-- i used this code:

process(CLK)
begin

if rising_edge(CLK) then

clock<=PS2_CLK;


if clock = '0' then

if enable='1' then
pulse<='1';
enable<='0';

else

pulse<='0';

end if;
else

enable<='1';

end if;

end if;

end process;