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xilinx EDK

Hi, i'm interested in using a can controller core in an spartan3e FPGA project. I'm using xilinx EDK right now, and I've seen a free can controller at opencores, but it uses a wishbone bus connection. I see they also have a wishbone to OPB bridge. Has anyone tried this before or know of a good tutorial/guide to get this working? Would there be any editing of code involved?

Thanks alot.