Initializing regs

FPGA projects on this site, or abroad

Initializing regs

Postby DJatPS » Fri Nov 13, 2009 1:25 am

I was looking through the debouncer code and being a good C programmer drilled to initialize all variables before use, was perplexed that the line of code:

begin
PB_cnt <= PB_cnt + 1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end

used PB_State assuming it was at zero. I don't see any place else that it is initialized. I know that you can't generally rely on gates powering up to any defined value but here it seems we are assuming PB_State will be zero when the module is entered. Is this safe?
DJatPS
 
Posts: 8
Joined: Fri Nov 13, 2009 12:43 am
Location: Arkansas

Postby Thoma HAUC » Fri Nov 13, 2009 7:53 am

Hi DJatPS,

Before all, the whole code is:

Code: Select all
always @(posedge clk)
if(PB_idle)
    PB_cnt <= 0;  // nothing's going on
else
begin
    PB_cnt <= PB_cnt + 1;  // something's going on, increment the counter
    if(PB_cnt_max) PB_state <= ~PB_state;  // if the counter is maxed out, PB changed!
end


And another point is that in SRAM based FPGA after configuration, the Flip-Flops are generally cleared.
Therefore, a lot of FPGA user never puts description to handle a true global clear.

In this case, after FPGA configuration has completed, PB_sync_0 equals 1'b0, PB_sync_1 equals 1'b0, PB_state equals 1'b0 and PB_cnt equals 16'b0. Now, you can do your behavioral analysis.

If you want to add a global clear (rst_n) then you can write for example:

Code: Select all
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else
q <= d;


Hope this help

Thoma
Thoma HAUC
 
Posts: 51
Joined: Thu Aug 26, 2004 4:57 am
Location: Near Paris, France


Return to General projects