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Dear ALL,

I have to measure time intervals with precision of 750 ns with FPGA.
Is there any known methods of doing this?
Will be gratefull for any ideas.

Thanks.

What do you mean by 'precision of 750m nSec' ? This should be re-phrased as something like:
" I wish to measure time intervals in the range xxx Sec to yyy Sec with a resolution of zzz Sec"

All that said, there are several ways to do this, but the two basic techniques are:

EITHER: Run a counter that is started by one end of your interval and stopped by the other. The _range_ is the length of the counter (not usually an issue in an FPGA) times the resolution and the _resolution_ is the counter's clock-period. The range of clock-rates available in an FPGA will give you lots of options here.

OR: Start a voltage-ramp (usually charging a capacitor with a current-source) at the beginning of the interval and hold its value at the end. Read the voltage with an A-D converter and convert to time. In this case, the range and resolution are both analog values. This method is more useful for very small time intervals and it will require calibration (i.e., measuring a known interval to characterize your hardware.)

I may even be necessary to combine the two methods: a rough, digital measurement followed by a high-accuracy analog measurement of the interval between your last measurement clock and the actual 'stop'-time

No matter how you do it, you will need to do some start/stop hardware design. Take my word for it, an FPGA makes this easy.

Good luck

Wade Hassler

For that resolution, you only need to have a clock running faster than 1.333 MHz. Design a set and reset logic circuit in the FPGA, where the start pulse sets the gate and the stop pulse resets the date. Count the number of clock cycles while the gate is high. At the end, convert number of clock cycles to time interval. Fairly easy with most FPGAs.

I will not go the route of charging a capacitor, unless you are trying to do pulse expansion. Not needed in this case.

Since precision is a function of all the factors contributing to the measurement, I would try and get the resolution much better than just the minimum to give me a safety factor for trigger errors and the one-count error.

If you are referring to accuracy, then you will need an accurate clock driving your FPGA. Again, easy.

1. As Kreeesh said, one definetly needs 1333 MHz (at least). That is not possible for me.

2. Analog methods are not aplicable as well.

So I am looking for interpolating method, like using phase shifted clocks,
to latch incoming signal by all of them.

My question was, is there any already working solution for that?

Just clear up this matter. Do you want 750ns, or 750ps precision. Your first post says 750ns, but the title suggest 750ps. There is a big difference between the two.

Ohh....
I am sorry for that.
of course I mean 750 ps.

750ps is definately a totally different beast. The only way is to combine a counter for the rough time interval and a pulse expansion technique for the least significant digits.

I know of two techniques.

The first involves charging a capacitor between the true start of the signal and the first clock signal. You do the same with another capacitor between the stop signal and the next clock signal. By discharging the two capacitors at a slower rate, one can calculate the time interval as a function of two currents. And one must also counter the number of clock cycles for the most significant bits.

The second involves a technique used by HP/Agilent where they start a second oscillator with a different frequency and then look when the two oscillators coincide again.

I found all this information using Google some time ago. Should still be available.

Kreeesh wrote:The first involves charging a capacitor between the true start of the signal and the first clock signal. You do the same with another capacitor between the stop signal and the next clock signal.

That's a fairly analog solution.

FPGAs make things a bit easier: you set up a tapped delay line consisting of elements of fixed delay (input/output time on the slices of the FPGA). String together enough of those elements to fit in a clock cycle of your clock, attach the taps to registered elements and clock them, and the pattern tells you when the signal occurred between the clock edges. Add that to the value counted by the clock edges, and you've got your time.

If you imagine having, say, a 50 ns clock, and delay elements of 10 ns each, and having 5 of them,

signal->del0->del1->del2->del3->del4

Suppose the signal happens at, say, 30 ns before the clock: in this case, del[4:0] would be 5'b11000.

Slice timing on FPGAs gets very fast, so you can have a very precise timing. 100 ps isn't that difficult with, say, a Spartan-3 (I know of solutions that have gotten less than 50 ps) using its fast carry chain.

It's of course not this easy - the delay varies with temperature and process, so you would want to set up a calibration circuit (where you string a bunch of your delay elements together and measure where successive clocks edges end up - multiple if you want more precision, etc). You also have to worry about metastability of the main counter, which you can get around by various tricks (use two counters on opposite clock phases, selecting the proper one based on the delay line - there are other less resource-intensive tricks).

But 750 ps isn't really that difficult. For the calibration circuit you could look at Xilinx's XAPP454 where they have a similar design, but for the opposite reason (generating a precise time interval).