fpga4fun.com

Hi,

I've been experimenting with FPGAs for a couple of weeks now and day after day my experiments are growing larger and larger. Unfortunately so are my synthesis and P&R times too .

Usually I'm tweaking the insides of a single VHDL module. Is there any way to tell the toolchain that it shouldn't resynthesize (and P&R) everything, but instead use the products of the previous round of synthesis and P&R, just like in software development the linker links previously compiled object files to make the actual executable?

I really don't care, if the result is little unoptimal as I'm nowhere near exhausting the capacity of the FPGA I use and the max speeds are still miles away from what I actually need.

I'm currently using Xilinx WebPack 11.1, but any tips on Quartus are also appreciated (as I'm hopefully going to get an Altera board soon).

Thanks in advance,
Juha

The feature you're looking for is called incremental compilation. I have not really used it, as up till now it has been a bit unpredictable, and Altera, last time I checked, was more advanced at this than was Xilinx. But things may have changed a great deal since I looked into ti.

r.b.