fpga4fun.com

I am a complete newbie when it comes to Verilog and FPGAs, having only received my first board (Digilent Nexys 2) earlier in the week.

I started out simply displaying the value of an 8-bit counter on the LEDs, and then moved on to the 7-segment displays. Displaying a single digit, or the same digit multiple times was simple enough, but my attempts at multiplexing haven't been so successful.

The intent of the code is to simply show the high and low nibbles of the 8 bit counter independently on two 7-segmenet displays.

When I run the code I see the same thing on both displays, sometimes the numbers are clear, and at other times other segments that should not be lit at all are dimly lit, making the numbers difficult to read.

I am interested in any and all feedback to assist with learning.

Thanks.

Code: Select all

`timescale 1ns / 1ps

module FPGAPlay(clk,LEDs,anodes,sevenseg);

   (* LOC="B8",PERIOD="50 MHz" *) input clk;
   (* LOC="R4,F4,P15,E17,K14,K15,J15,J14" *) output reg [7:0] LEDs=0;
   (* LOC="F17,H17,C18,F15" *) output reg [3:0] anodes=15;
   (* LOC="L18,F18,D17,D16,G14,J17,H14,C17" *) output reg [6:0] sevenseg=0;

   reg [7:0] cnt = 0;
   reg [3:0] digit = 0;
   reg [23:0] delay = 0;
   reg [0:0] seg = 0;
   
   always @(posedge clk) begin
      if(!delay) begin
         cnt=cnt+1;
         LEDs=cnt;
      end
      case (seg)
         1'b0 : anodes=4'b1011;
         1'b1 : anodes=4'b0111;
      endcase
      case (seg===0 ? (cnt & 8'hF0) >> 4 : cnt & 8'h0F)
         8'h0 : sevenseg=7'b0000001;
         8'h1 : sevenseg=7'b1001111;
         8'h2 : sevenseg=7'b0010010;
         8'h3 : sevenseg=7'b0000110;
         8'h4 : sevenseg=7'b1001100;
         8'h5 : sevenseg=7'b0100100;
         8'h6 : sevenseg=7'b0100000;
         8'h7 : sevenseg=7'b0001111;
         8'h8 : sevenseg=7'b0000000;
         8'h9 : sevenseg=7'b0000100;
         8'hA : sevenseg=7'b0001000;
         8'hB : sevenseg=7'b1100000;
         8'hC : sevenseg=7'b0110001;
         8'hD : sevenseg=7'b1000010;
         8'hE : sevenseg=7'b0110000;
         8'hF : sevenseg=7'b0111000;
         default : sevenseg=7'b1111110;
      endcase   
      seg = seg + 1;
      delay <= delay + 1;
   end
endmodule


Hello. It looks like you have the right idea, but you're driving the display too fast.

When you toggle the anode and sevenseg outputs, the FPGA pins don't change voltage instantly... they take a few nanoseconds to rise and fall. The anode transistors will also slow things down. During the "crossover", you could be driving the wrong segments dimly. At 50MHz the whole thing could be a blur.

Try changing "seg = seg + 1" to something like "if (!delay[15:0]) seg = seg + 1".

Nick

Thank you for that. The suggested change worked nicely, and I now have renewed confidence in behing able to get my head around hardware design.