fpga4fun.com

I've been trying to modify the RS-232 Interface example project to simply echo received characters back, instead of sending the status of a switch bank or whatever.

I've tried several different things, but basically end up with various errors like

Code: Select all

ERROR:HDLCompilers:247 - "async_receiver.v" line 96 Reference to vector wire 'passtoxmit' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "async_receiver.v" line 96 Illegal left hand side of nonblocking assignment


because I'm unsure of how exactly to form a connection between the two different modules.

I tried creating a local wire when I instantiate the modules, and then passing that into each of the modules, but that hasn't worked either.

Can someone point me in the right direction?

Thanks

Keith

I always run into those errors when I move an assignment from outside an always block:

Code: Select all

wire new_signal;

assign new_signal = whatever_combo;

into an always block:

Code: Select all

always @(posedge clk)
  new_signal <= whatever_combo;

You need to change the wire into a reg:

Code: Select all

reg new_signal;