fpga4fun.com

I am a post-graduate student at the University of Ioannina Greece "Physics department". My thesis subject has to do about an implement of SDR receiver and demodulation of fm signal. I already have implement the DDC part in an FPGA with my I and Q signals in two complement's integer format (the same format used by the ADC) but i have problem with the demodulation and especially with division.I use a Digital Phase Discriminator algorithm witch produce an output following the next equation (I*dQ – QdI)/(I^2 + Q^2).I can compute the numerator and the denominator but the problem is with division. I can use a divisor but the result from this division is just a quotient and a remainder, this wont give the desired output in a fixed scale capable to be processed properly by a DAC.Is there any possible way to implement a divisor with a fixed range quotient in regard with the remainder.In other words is it possible to produce an approximated quotient from the division of two complement format signals. with only the knowledge of the first quotient and the remainder, and if that is possible what is the form of the output?Any answer guidance proposed bibliography or links will be very helpful.

Without getting into the analytic part - if it's possible to do with C for example, you can use SOPC and do it on your fpga.

What do you want to do with the reminder? could you give an example because I'm not sure what you want to get as a result...