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Hi,

I'm working on a project that is powered by a 12V battery. The power button can be turned off at anytime. My problem is that when the power button is switched off I need approx. 3 seconds more of full power to properly shut down.

Any ideas, procedures, or thoughts would be greatly appreciated.

Thanks

Hi David,

Here's one way to do it: Use a Power PMOS transistor as the main switch. The "on/off" button pulls the gate low, and also connects to a microcontroller input. Use diodes to isolate these two functions; or use a 2-pole switch. The microcontroller has an output which controls a NMOS transistor, which it can use to hold the power "on" until it decides to kill itself.

Code: Select all

Batt --+---------- PMOS ---------> Power
+12V   |         s g|  d
       |            |
       +--/\/\/\----+     +-----<- 5V or 3.3V
           33K      |     |
                    /     /
                33K \     \ 4.7K
                    /     /
                    |     |
          +---------+     +-----> digital input
          |         |     |
digital   |         V     V
output    |         -     - diodes
->-+--- NMOS        |     |
   |      |         +-----+
   \      |         |
   / 2.2K |          |- Switch
   \      |         |
   |      |         |
  GND    GND       GND

Nick

P.S. If it's an FPGA project, I guess you can make this circuit with an FPGA instead of a microcontroller... but FPGAs take a while to configure, so better use a toggle-switch rather than a pushbutton (to avoid false starts and glitches). Also, you could use a relay instead of a PMOS.

Thanks Nick,

I think this circuit is going to work great. However, I'm unfamiliar with the PMOS transistor. I looked at a couple of datasheets and they list the Gate-to-Source threshold voltage as -2.0(min) to -4.0(max) volts. I understand the Gate-to-threshold voltage to be the point the transistor switches. From your circuit the two 33K resistors create a voltage divider circuit. Allowing 6V to appear at the transistors gate terminal when the user switch is open. When the user switch is closed it creates a direct route to ground effectively allowing 0V to appear at the transistors gate terminal. Is this correct? Can you explain why the voltages of the Gate-to-Source threshold are negative or how this PMOS works in this circuit. I'm having a problem with these negative voltages.

david119

Hi David,

When everything's powered down, voltage at the gate (and the whole middle part of the circuit) will be 12V (Vgs = 0); hopefully no current flows anywhere. When the switch and/or the NMOS transistor is on, a voltage divider is formed, and gate voltage goes to about 6V (Vgs = -6V relative to the source, because the source terminal is more positive), turning the PMOS on to conduction.

BTW my resistor values were off the top of my head. I don't think they're critical. The middle 33K resistor could probably be reduced, if it was a 9V battery or you wanted larger -Vgs. But don't omit it altogether, as it helps prevent a short in case of component failure... A fuse on the battery terminal might be a good idea, too.

It should work as it is, but if your digital logic thrashes around during power-down* I guess it's possible you might need to reduce the 2.2K resistor or put some kind of filter on the control signal.


Nick

* Anybody know if FPGAs can misbehave when the power fails?