fpga4fun.com

Hello group,

After reading the description from http://www.fpga4fun.com/SerialInterface.html I've implemented the uart in my code. I have a question, how can i use RxD_data_ready and TxD_busy vars. Can i reroute them to a pin so i can detect when transmission is busy or when a character is received ?

Thanks in advance,
Zuurcool

sure, you can do that.

Hello,

Thanks for your reply, is there any existing code how to implement this or can you give me a little bit more info how to configurate this ?

Thanks,
Zuurcool

Because i'm a bit in the dark about how to detect when i can read the received byte and when i can send a byte.

Since it's (as far as i can see) the same memory place

Zuurcool

You do seem confused.

I think you need to experiment a little and things should lighten up.
Do you have an FPGA board? try to program a simple RxD or TxD separately, or try the example I give here
http://www.fpga4fun.com/SerialInterface5.html
and go from there.

Hello,

Thanks for pointing out i'm a bit confused

I would like to start then with the receive part, i've used the example at http://www.fpga4fun.com/SerialInterface5.html and only enabled the receive instance. Then i use the following code to get a status from the module

always @(posedge clk)
if (addr == 0)
GPout <= RxD_data;
else if (addr == 1)
begin
GPout <= {4'b0000, RxD_endofpacket, RxD_idle, RxD_data_ready, TxD_busy};
end
else
GPout <= 8'hxx;

Now i would like to check when a byte is received, so i check the second bit from this status, but it is never set ?

Greetings,
Zuurcool.

You seem to use a CPU.
You have an "addr" bus and you created 2 registers.

The problem is that "RxD_data_ready" is valid for only one clock period. It's fine for an FPGA state machine that would monitor this bit, but not for a CPU. You'd need to be very lucky to have the CPU check the register at the exactly the right time the RxD_data_ready bit is set.

You need to create something like "RxD_data_available" that would be valid when data is available and until you read it. Also you might need to register the data because if new RS232 data starts coming before you read RxD_data, it might disturb the current RxD_data.

Try something like (this is not tested)

Code: Select all

reg [7:0] RxD_data_reg;
always @(posedge clk)
if(RxD_data_ready)
  RxD_data_reg <= RxD_data;

reg RxD_data_available;
always @(posedge clk)
if(RxD_data_available==0)
  RxD_data_available <= RxD_data_ready;
else
  RxD_data_available <= ! "the cpu is reading the RxD_data_reg";


I've been testing a bit and have a working situation, i couldn't monitor a single bit so i've used a counter, now i can detect if i received a character and check if i missed one.

Thanks for your help

For transmit & recieve data from PC to board FPGA, we can use CORE UART - seem ready for all board...easy & rely^.^