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Can a logic be implemented for the code written below:

module test( clk1,
clk2,
clk3,
a,
b,
c,
d);


input clk1;
input clk2;
input clk3;
input a;
input b;
input c;
output d;


always @(posedge clk1 or posedge clk2 or posedge clk3)
begin
if (clk1)
d <= a;
else if (clk2)
d <= b;
else if (clk3)
d <= c;
end
endmodule

What I really want to do in hardware is to change the value of 'd' only when either of the three clock edges(clk1,clk2,clk3) happen. Is it possible to create such a logic on hardware ?

Regards,
Kapil

I tried something like that and I could not get it to work.

My clocks were out of phase and generated by multiple oscillator modules. Eventually, the edes line up much like waves in a guitar chord and this is when the inputs fail, or miss pulses. Even a 20MHz and 10MHz the timing will eventually cause failures unless the pulses are derived from a divider.

I finally figured it like this...

Imagine 3 people are throwing you baseballs. As long as the balls arrive at different times, you can probably keep up. But what happens when all 3 balls arrive at once, or so close together that you can't handle them all at once...... lost balls.

I guess if you were really good, some kind of filter or clock pulse buffer could be used, but that is way over my head.

Good luck.

Brad

Brad, I understand what you are trying to say. You basically want to say that timing failures will cause this circuit to not work. However, my doubt is that is there a hardware possible at all even if clk edges come at different times? I tried to synthesize the code that I have written above in Xilinx and logic it implemented used only a single D flop and by close examination i discovered that it is not completely doing what i intend it to. The logic is such that output changes even if none of clk edges happen.

Although I did not use the same code as you have, I did try to read 2 differing clock sources and create an event that would happen when both were on the posative edge. For my application, the failures would happen when two edges eventually came into phase and violated input times.

My main clock was 40MHz and the other one ranged from 1MHz to 20MHz, depending on the host device. Eventually, my only solution was to up the CPLD clock to 80 or 100MHz and keep the host no more than 20MHz. This way the resolution of the input was much higher.

Yes, it was a strange project, but I could not have a syncro. clock.

Brad

Think about that you are trying to do from a hardware perspective. You are using three unrelated clocks of different frequencies in a synchronous system, where setup and hold times still have to be met. However, you have absolutely no way of assuring these can be met, since no signal has a fixed relationship to another. This violates the basic definition of synchronous. Thus, implementing the circuit the way you have, you will never have a predictable value of D. Synthesis won't really care, especially if you have provided no timing contraints. It'll make a best guess and assume all the clocks are equal and reduce it to single flip flop.

If you truly want to do this, you will need to put 'd' in one clock domain, and generate control signals from the other two clock domains, metastability harden them into the d clock domain, and then use them to change the state of 'd'. However, this may still not give you the output you seek, given the inherent delay in metastability hardening. It will work best if the clock domain used to clock the 'd' output is many times faster than the other two.



r.b.