by rberek » Fri Nov 28, 2008 5:59 pm
Think about that you are trying to do from a hardware perspective. You are using three unrelated clocks of different frequencies in a synchronous system, where setup and hold times still have to be met. However, you have absolutely no way of assuring these can be met, since no signal has a fixed relationship to another. This violates the basic definition of synchronous. Thus, implementing the circuit the way you have, you will never have a predictable value of D. Synthesis won't really care, especially if you have provided no timing contraints. It'll make a best guess and assume all the clocks are equal and reduce it to single flip flop.
If you truly want to do this, you will need to put 'd' in one clock domain, and generate control signals from the other two clock domains, metastability harden them into the d clock domain, and then use them to change the state of 'd'. However, this may still not give you the output you seek, given the inherent delay in metastability hardening. It will work best if the clock domain used to clock the 'd' output is many times faster than the other two.
r.b.