The part is CY7C1049CV33 or DV33, I was just referring to the CYC series generally.
http://www.ociw.edu/instrumentation/ccd/parts/CY7C1049CV33.pdf
In the datasheet, the usual RW timings are given, which are basic for all SRAMs. Notice how not once does it mention bus turnaround times.
If it wasn't for the fact that I have a working system here, I would also belive you that there is no such timing consideration. It took days to finally sort out small glitches that I once thought were in my code, but in fact were bus turnaround times.
All I did was add 2 dead cycles after the horizontal pixel read, which buffers 256 pixels into a blockram before allowing RW access to the ram. It was strange... reading worked right away once the "memready" flag was set, but the first two writes would be random or glitchy.
After much digging, I found several other people who have discovered this problem when using SRAM near it's maximum ratings.
When I read this it made me think...
http://www.eeherald.com/section/design-guide/esmod15.html
>>
ZBT (zero bus turnaround): the turnaround is the number of clock cycles it takes to change access to the SRAM from write to read and vice versa. The turnaround for ZBT SRAMs or the latency between read and writes cycle is zero. In short the ZBT is designed to eliminate dead cycles when turning the bus around between read and writes and reads.
>>
So I simply added 2 dead cycles between the last buffer read and the "memready" flag and it solved all problems instantly.
To further test this dead cycle fix, I upped the master clock from ~60MHz to 100MHz and found that I indeed needed 3 cycles, just as someone on another site pointed out when using SRAM at 10ns.
I can't be the only person here that has discovered that bus SRAM turnaround time is real?? I guess if it wasn't a real issue, IDT would not have created ZBT SRAM.
Here is a tiny bit of code from my GPU section that does a block copy from one page of memory to another...
- Code: Select all
/////////////////////////////////////////////////////////////////////////////////////////////////
////////// COMMAND 015 - BLOCK COPY : (ROTATION VALUE : ALPHA COLOR)
////////// X1LOC,Y1LOC : SOURCE X1,SOURCE Y1
////////// X2LOC,Y2LOC : SOURCE X2,SOURCE Y2
////////// X3LOC,Y3LOC : DESTINATION X,DESTINATION Y
////////// X4LOC,Y4LOC : SOURCE PAGE,DESTINATION PAGE (100 = CURRENT DRAWING PAGE)
/////////////////////////////////////////////////////////////////////////////////////////////////
if (rxcomm == 15 & comstate == 1) begin
deltax <= x1loc;
// SELECT POSITION 0
if (rxdata1 == 0) begin
deltay <= x3loc;
end
// SELECT POSITION 1
if (rxdata1 == 1) begin
deltay <= y3loc;
x3loc <= x3loc + (x2loc-x1loc);
end
// SELECT POSITION 2
if (rxdata1 == 2) begin
deltay <= x3loc + (x2loc-x1loc);
x3loc <= x3loc + (x2loc-x1loc);
y3loc <= y3loc + (y2loc-y1loc);
end
// SELECT POSITION 3
if (rxdata1 == 3) begin
deltay <= y3loc + (x2loc-x1loc);
y3loc <= y3loc + (x2loc-x1loc);
end
// SELECT POSITION 4
if (rxdata1 == 4) begin
deltay <= x3loc+ (x2loc-x1loc);
x3loc <= x3loc + (x2loc-x1loc);
end
// SELECT POSITION 5$$
if (rxdata1 == 5) begin
deltay <= y3loc + (y2loc-y1loc);
x3loc <= x3loc + (x2loc-x1loc);
y3loc <= y3loc + (x2loc-x1loc);
end
// SELECT POSITION 6
if (rxdata1 == 6) begin
deltay <= x3loc;
y3loc <= y3loc + (y2loc-y1loc);
end
// SELECT POSITION 7
if (rxdata1 > 6) begin
rxdata1 <= 7;
deltay <= y3loc;
end
// CALCULATE SOURCE AND DESINTATION PAGES
xtemp <= x4loc*51200;
if (y4loc < 100) ytemp <= y4loc*51200;
if (y4loc == 100) ytemp <= drawpage;
comstate <= 2;
end
// EXECUTE COMMAND PIPLINE FOR BLOCK COPY
if (rxcomm == 15 & comstate == 2 & memready == 1) begin
pipeline <= pipeline + 1;
// PIXEL READ CYCLE
if (pipeline == 2) begin
sramadr <= x1loc+(y1loc*256)+xtemp;
sramwe <= 1;
sramoe <= 0;
sramce <= 0;
end
if (pipeline == 4) delta <= sramport;
// PIXEL WRITE CYCLE
if (pipeline == 5) begin
sramout <= palette[delta];
sramadr <= x3loc+(y3loc*256)+ytemp;
sramwe <= 0;
sramoe <= 1;
sramce <= 1;
end
// BLOCK COPY MATH FOR POSITION 0
if (rxdata1 == 0 & pipeline == 6) begin
x1loc <= x1loc + 1;
x3loc <= x3loc + 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
x3loc <= deltay;
y1loc <= y1loc + 1;
y3loc <= y3loc + 1;
end
end
// BLOCK COPY MATH POSITION 1
if (rxdata1 == 1 & pipeline == 6) begin
x1loc <= x1loc + 1;
y3loc <= y3loc + 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
y3loc <= deltay;
y1loc <= y1loc + 1;
x3loc <= x3loc - 1;
end
end
// BLOCK COPY MATH FOR POSITION 2
if (rxdata1 == 2 & pipeline == 6) begin
x1loc <= x1loc + 1;
x3loc <= x3loc - 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
x3loc <= deltay;
y1loc <= y1loc + 1;
y3loc <= y3loc - 1;
end
end
// BLOCK COPY MATH POSITION 3
if (rxdata1 == 3 & pipeline == 6) begin
x1loc <= x1loc + 1;
y3loc <= y3loc - 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
y3loc <= deltay;
y1loc <= y1loc + 1;
x3loc <= x3loc + 1;
end
end
// BLOCK COPY MATH FOR POSITION 4
if (rxdata1 == 4 & pipeline == 6) begin
x1loc <= x1loc + 1;
x3loc <= x3loc - 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
x3loc <= deltay;
y1loc <= y1loc + 1;
y3loc <= y3loc + 1;
end
end
// BLOCK COPY MATH POSITION 5
if (rxdata1 == 5 & pipeline == 6) begin
x1loc <= x1loc + 1;
y3loc <= y3loc - 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
y3loc <= deltay;
y1loc <= y1loc + 1;
x3loc <= x3loc - 1;
end
end
// BLOCK COPY MATH FOR POSITION 6
if (rxdata1 == 6 & pipeline == 6) begin
x1loc <= x1loc + 1;
x3loc <= x3loc + 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
x3loc <= deltay;
y1loc <= y1loc + 1;
y3loc <= y3loc - 1;
end
end
// BLOCK COPY MATH POSITION 7
if (rxdata1 == 7 & pipeline == 6) begin
x1loc <= x1loc + 1;
y3loc <= y3loc + 1;
if (x1loc == x2loc) begin
x1loc <= deltax;
y3loc <= deltay;
y1loc <= y1loc + 1;
x3loc <= x3loc + 1;
end
end
// FINISH PIPELINE
if (pipeline == 6) begin
if (x1loc < x2loc | y1loc < y2loc) pipeline <= 0;
if (delta != rxdata2) begin
sramwe <= 0;
sramoe <= 1;
sramce <= 0;
end else begin
sramwe <= 1;
sramoe <= 1;
sramce <= 1;
end
end
// COMPLETE COMMAND
if (pipeline == 7) begin
sramwe <= 1;
sramoe <= 1;
sramce <= 1;
rxcomm <= 0;
pipeline <= 0;
hostak <= 1;
end
end
Notice that the pipeline must jump from 2 to 4 during the transition between read and writes, allowing 2 dead cycles for bus turnaround time. Without this latency, the first few writes are random or fail.
This took days to figure out.
Oh well, my system is almost ready for manufacture now, and I am sticking with.... bus turnaround time is real!
Brad
