fpga4fun.com

hi, i would like to know how logic behaves in a real fpga(not a simulator).
say, i had a 3-bit counter connected to a 3-8 line decoder and each output line was connected to an input of the same OR gate, in theory, the output of the OR gate should stay at 1 as the counter is incremented.
will this really work like this, or will each counter transition cause some glitch in the output which could possibly trigger a flipflop?

thanks for any replies.

Lee

Hi Lee,

Yes, there could be a glitch! It's called a Static hazard. Another classic example is a multiplexer: (a?b:c) might glitch when a changes even if b and c are the same.

Usually, it's not a problem. It's safe to use the output as input to another Flipflop on the same clock. But it's not safe to use it as a clock, or as an asynchronous control signal for anything. If you need to do that, the solution is to put another Flipflop on the output. This delays it by one cycle.

BTW, It's a good idea to ensure all chip outputs or derived clocks come directly from a Flipflop, or the negation of a Flipflop. [It's sometimes possible to make logic "glitch-proof", but it's hard to express it in Verilog or VHDL -- the tools may "optimize out" your attempts to make it safe -- and remember FPGAs don't use normal gates.]

Nick

ah, i see. how about something as simple as using a AND gate to stop a counter incrementing. ie: a clock ANDed with a line which is at 0. would that glitch at the clock transitions? if so, how can i do this properly?

You need to be aware that when you AND a clock with another signal, the new signal becomes a potential clock signal. If the inhibit/enable signal pulses when the clock is low, you get another clock edge at the gate's output.

ok, how about an inverter on the clock?

the main problem im having is producing glitch free timing lines, such as T1-T8 from harry porter's relay computer:
http://web.cecs.pdx.edu/~harry/Relay/Re ... age195.png
how would this be done without a risk of a glitch?

I'm a bit confused what you're trying to do: are these internal signals in your FPGA, or are they driving off-chip...?

In your example, you can make 8 individual outputs glitch-free: simply register them using flipflops. But you can't guarantee they'll switch simultaneously (it's impossible to define, because it takes time to get from 0 to 1, and the wires will have tiny, different delays on them).

If it's for on-FPGA use, don't try to use them as clocks, but use them as enables. For instance:

Code: Select all

always @(posedge clock) begin // generate enabling pulse every 8th cycle
  counter <= counter + 1'b1;
  t1 <= (counter == 3'b000);
end

always @(posedge clock) begin
  if (t1) begin
    foo <= bar; // foo gets updated after the cycle when t1 was high
    something <= else + other;
    // etc...
  end
end

Just distribute the enable signal "t1", alongside "clock", to all the modules that need it. [Make sure the enable is registered, because that helps with fanout issues.]

FPGAs are intended for this sort of "synchronous" design. Trying to use them in other ways is a bit of a struggle!

Regards,

Nick