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Hello All,
I have been trying to place and route a FPGA code but PAR is not completing the operation. It always stops in the middle without giving any reason. In the end, it just says that design is not completely routed. The design passes sythesis & mapping without any problems.
Below is the message which I recieve when PAR starts.
Starting Placer

Phase 1.1
Phase 1.1 (Checksum:99343e) REAL time: 7 secs

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 7 secs

Phase 3.2
Phase 3.2 (Checksum:1c9c37d) REAL time: 8 secs

Total REAL time to Placer completion: 12 secs
Total CPU time to Placer completion: 11 secs


Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 0/done_SPI* | Global| No | 22 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| IntAdcClk80M* | BUFGMUX_X0Y6| No | 41 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 1/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 2/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 0/SPCLK* | BUFGMUX_X1Y10| No | 42 | 0.074 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 3/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 4/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 5/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| SramOE_OBUF* | Global| No | 65 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| write_strobe* | BUFGMUX_X0Y3| No | 329 | 0.074 | |
+---------------------+--------------+------+------+------------+-------------+
|instRegister/instSPI | | | | | |
| 0/spiclk<1>* | Global| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| picoclk* | BUFGMUX_X0Y7| No | 73 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instembedded_kcpsm3/ | | | | | |
| prog_rom/drck1_buf* | BUFGMUX_X0Y2| No | 4 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk_i* | BUFGMUX_X0Y5| No | 376 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| clk_div_2* | BUFGMUX_X0Y4| No | 66 | 0.074 | |
+---------------------+--------------+------+------+------------+-------------+
|instembedded_kcpsm3/ | | | | | |
| prog_rom/update* | BSCAN| No | 1 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instdedicated_upload | | | | | |
|/instRS232_upload/ba | | | | | |
| ud_rate* | Global| No | 11 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instUART_Tx/baud_rat | | | | | |
| e* | Global| No | 5 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instdedicated_upload | | | | | |
|/instmemory_controll | | | | | |
| er/write_strobe* | Global| No | 5 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|instasync_receiver/d | | | | | |
| one* | Global| No | 17 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
* Some of the Clock networks are NOT completely routed

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0

Generating Pad Report.

3974 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.

Total REAL time to PAR completion: 23 secs
Total CPU time to PAR completion: 19 secs

Peak Memory Usage: 187 MB

Placement: Completed - errors found.
Routing: Completed - errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0

Writing design to file toplevel.ncd

Regards,
Kapil Kesarwani

kapil.kesarwani wrote:Hello All,
I have been trying to place and route a FPGA code but PAR is not completing the operation. It always stops in the middle without giving any reason. In the end, it just says that design is not completely routed. The design passes sythesis & mapping without any problems.
Below is the message which I recieve when PAR starts.
Starting Placer

Phase 1.1
<...>
3974 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.
<...>
Number of warning messages: 2

What's the other warning? Do the logs from MAP or translate give any hints?

Marc

NO, that is what the worst part is ..none of the other process gives and warnings that might point in this direction.

kapil.kesarwani wrote:NO, that is what the worst part is ..none of the other process gives and warnings that might point in this direction.

The message at the bottom of the log you included said "Number of warning messages: 2". Are you saying that this line is a mistake and it should say only 1?

Marc

The first warning is that design is not completey routed and the other one says that this is only an evaluation version of ISE and it will expire in 54 days.

kapil.kesarwani wrote:The first warning is that design is not completey routed and the other one says that this is only an evaluation version of ISE and it will expire in 54 days.

I would create a completely different project with a VERY simple design to verify the tools are working. Then slowly pull in portions of your design to figure out what is causing the tools to barf. A bug in the tool is quite possible, but in my experience, it is equally likely the code has a problem.

Marc

yeah i tried to do that, it seems as I increase the no. of IOs used on bank 0, the tool starts giving the above mentioned problem. The log says placement has error but doesnt tell what error

The problem was with the placement. It seems the tool was not able to place properly with so many IOs occupied in one bank(~100%). Also I was taking a differential clock as input. So I guess tool was not able to place differential buffers along with lots of bi directional buffers in one place. So i just changed the position of DCM to which differential clocks were going. It seems to have solved the problem as of now. Also few ports on toplevel code were not assigned in UCF. This also was causing trouble.

kapil.kesarwani wrote:The problem was with the placement. It seems the tool was not able to place properly with so many IOs occupied in one bank(~100%). Also I was taking a differential clock as input. So I guess tool was not able to place differential buffers along with lots of bi directional buffers in one place. So i just changed the position of DCM to which differential clocks were going. It seems to have solved the problem as of now. Also few ports on toplevel code were not assigned in UCF. This also was causing trouble.

100% utilization by itself likely wasn't the problem, but perhaps the 100% utilization in combination with clock input(s) was.

Have fun,

Marc