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I am using Board FPGA Spartan3 and want to readback using JTAG TDO pin, the following is part of my source code (based on the TAP state machine):
My question is that it seems that no data is clocked out of the TDO pin

process (JCLK)
begin

if rising_edge(JCLK) then
.........................
...............................

if (COUNTER = 17) then -- IDCODE Bit 5=0
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 19) then --IDCODE Bit 6 (MSB)=0 --Exit-IR1
TMS <= '1'; --Update-IR --Select-DR-Scan
TDI <= '0';
end if;
if (COUNTER = 25) then --Capture-DR --Shift-DR
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 29) then --
TMS <= '0';
DATAOUT_SIG(0) <= TDO;
end if;

if (COUNTER = 31) then
TMS <= '0';
DATAOUT_SIG(1) <= TDO;
end if;

TDO is definited in the entity as : in std_logic; --Test Data Out
and DATAOUT_SIG is signal of 32 bits width.

Can any one perhaps tell me where is wrong with this using style of readback IDCODE?

traeumerling wrote:I am using Board FPGA Spartan3 and want to readback using JTAG TDO pin, the following is part of my source code (based on the TAP state machine):
My question is that it seems that no data is clocked out of the TDO pin

<...>

TDO is definited in the entity as : in std_logic; --Test Data Out
and DATAOUT_SIG is signal of 32 bits width.

Can any one perhaps tell me where is wrong with this using style of readback IDCODE?

Howdy traeumerling,

The real TDO pin is not a user-defined I/O, which means you can't control it like you are talking about doing. The JTAG pins are controlled by a non-configurable JTAG state machine that is built-in.

IDCODE type stuff is typically done in your bitstream during bitgen.

I'm curious though - what pin number do you have defined in your .ucf file for your TDO net? If it is the same as the real TDO pin, I would have expected the tools to error out.

Marc

Hi, in my UCF file I constraint the JTAG pins to extension ports. I donot think there shouldbe wrong. Also I can show u my part of UCF file here as the following: (Design tools r EDK and ISE)

#### Module opb_s3icap_0 constraints
#Expansion Connector A2 von rechts nach links
#GND
#VCC
#TMS
#TDI
#TDO
#TCK
Net opb_s3icap_0_JTAG_TMS_pin LOC=d5;
Net opb_s3icap_0_JTAG_TDI_pin LOC=d6;
Net opb_s3icap_0_JTAG_TDO_pin LOC=e7;
Net opb_s3icap_0_JTAG_TCK_pin LOC=d7;

I did not control TDO, just want to read the data which appear on TDO after IDCODE instruction shown in UG332

Will U please help me?

Waiting eargerly for replying!

traeumerling wrote:Hi, in my UCF file I constraint the JTAG pins to extension ports. I donot think there shouldbe wrong. Also I can show u my part of UCF file here as the following: (Design tools r EDK and ISE)

#### Module opb_s3icap_0 constraints
#Expansion Connector A2 von rechts nach links
#GND
#VCC
#TMS
#TDI
#TDO
#TCK
Net opb_s3icap_0_JTAG_TMS_pin LOC=d5;
Net opb_s3icap_0_JTAG_TDI_pin LOC=d6;
Net opb_s3icap_0_JTAG_TDO_pin LOC=e7;
Net opb_s3icap_0_JTAG_TCK_pin LOC=d7;

I did not control TDO, just want to read the data which appear on TDO after IDCODE instruction shown in UG332

Will U please help me?

Waiting eargerly for replying!

Ok, so when you talked previously about the TDO and TDI lines, you are actually talking about general purpose I/O, and you are emulating the JTAG TAP machine rather than using the one built-in to the FPGA. Is that all correct?

Have you simulated your code?

Marc

P.S. Please don't repeat your question in multiple areas of the forum. You might consider reading http://catb.org/~esr/faqs/smart-questions.html