Hi everyone,
Sorry to revive an old thread but I see the OP's question was never answered and I am actually wondering the very same thing.
I can tell you the easiest way if you are using Xilinx ISE and a Xilinx based FPGA is to instantiate a BSCAN primitive in your verilog design and then hook up your own register to that primitive's interface.
Here is a pretty well-documented example from one of MIT's digital design lab courses:
http://web.mit.edu/6.111/www/f2005/code ... mem.v.html
For more reading, read XAPP139 from the documentation on Xilinx's website. Now Xilinx also includes a TCL interface to communicate to the cable you are using through a TCL script so in this manner you can transfer data from your PC to your design on the FPGA.
However, it is well known that Xilinx's TCL-to-JTAG interface is VERY slow (some user reported 30 minutes to send 16MB of data to the FPGA) so I am looking for a way to bypass Xilinx's TCL interface and directly drive the cable with my data via C/C++, hopefully at a much faster data rate. I've done a lot of reading about how Xilinx's cable drivers are a proprietary nightmare and accessing them is nearly impossible. Has anyone had any luck?
