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hi, i have two processes in my code to do things during the rising edge and the falling edge of the clock pulse. i capture two signals, one from rising edge and the other from falling edge, on the oscilloscope and found that the 2nd one is lagging the 1st one by abt 10ns (period of clock pulse is 20ns). however i was told to check if the 10ns delay is due to my coding or due to the process delay of the FPGA. so now i wants to capture the master clock signal and compare it with the other two signals to identify if the 10ns lag is due to process delay. but how can i capture the master clock signal? i cant find the pin on the FPGA board that is for the clk. how can i tap the master clock signal? i am using the XEM3010 board. please help.. or if there is another way of checking the lag/delay, please advise. thanks a million...

What's your master clock frequency?

At 50 MHz, you get a rising edge every 20ns, and a falling edge every 20ns. If the clock has 50% duty cycle, it will spend about 10ns in '1' state and about 10ns in '0' state.

Your compiler software should be able to give you a very accurate report of delays. A 10 ns logic delay is a lot, for that to happen your code must be very unusual.

Since 10 ns is the delay between rising and falling edge it suggests that you did a simple mistake or are just confused about how to interpret the results. So check out those two likely problems before go looking for something unlikely.