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My design includes one data generator and one router, router part is 100% ok. I add a counter in the FSM of data generator to count the number of trasmitted data. Each time the data generator receives a acknowledge of tx, the counter is added by 1.

It runs correctly in Modelsim behavior simulation and also on FPGA after configuration without any area constraint.

The problem is that when I add two area constraints for the data genearator and the router, which are hoped to be some distance(about 40 slices) apart, the counter works incorrectly sometimes.

I use the ChipScope to observe, the counting register counts correctly for many time until it crashes, as it counts to 1, then back to 0, then 1, 2, 3, 4... , though all the other signals are all right as modelsim simulation and the change of FSM states is all right too.

I can't figure it out. Pls help me.

Problem already solved, timing error