fpga4fun.com

Hi ALL,

Just curious...

Using HDL like Verilog or VHDL, is there a way to modify, simulate, and/or compensate and adjust main FPGA clock frequency?

For example, I want to slowdown my code from 48MHz to 26MHz using an Altera Cyclone I (EP1C12Q240C8N).

I probably could use registers as counter/flag to match my target frequency,but I am just wondering if someone had a better solution instead of changing the clock IC on the PCB.

Thank you all in advance!

-- TVZ

EP1C12 has built-in PLL hardware that can be used to change the clock rate. I don't know how to configure it, though.

[Or you could do it in Verilog with a counter and control bit, as you describe... but you'd still have to synthesize the design for 48MHz, and external devices would see irregular waveforms. So I think it's better to use a PLL.]

Nick

A PLL can be generated by the MegaWizard Plug-In manager from Quartus. If it's done correctly, you will describe a PLL that takes your 48MHz input clock and multiplies it by 13/24, resulting in 26MHz for use in the device.
If you ask that a Verilog file be created, you will find that the following 'instantiation template' is created: (its file name in this case is 'sample_PLL_inst.v')

sample_PLL   sample_PLL_inst (
    .inclk0   ( inclk0_sig ),
     .c0      ( c0_sig )
      );

To use the template in a Verilog project:
    Give it a unique name
    Replace 'inclk0_sig" above with your 48 MHz
   Connect 'c0_sig' as your 26MHz source.

It will look something like this:

My_PLL    sample_PLL_inst (
     .inclk0     (48_MHz_Oscillator_input),
     .c0         (New_26_MHz_Clock_Source)
     );

.. there will be another file created (called, in this case, 'sample_PLL.v') that contains the actual code for the PLL, but you only need to make sure that it is located on a path that the compiler can find.


There are a lot of details to using the MegaWizard-etc, though... it took me a while to be able to generate a file with only the outputs I wanted.

Wade Hassler