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Hi, I have a problem that I'm not understanding in Verilog. Hopefully I have simplified it and it still makes sense.

I create a wire and connect to an inout in another module. That wire is always driven from my module. But it doesn't work. However, when I add a debug line to send it, it starts to work. Below is a stripped down bit of code that hopefully illustrates the issue.

---
module X
(
output wire [7:0] DebugOut
)

// Register to hold the data to write
reg [31:0] DataToWrite
wire [31:0] MyData

// Define a module. Note that .Data is defined in ExtModule as inout wire [31:0] Data
ExtModule MyModule(.Data(MyData) );

// If this line below is uncommented, it works as expected. If I comment it out, the value written to ExtModule is usually all '1'
assign DebugOut = MyData[15:8];

// If we're in a certain state, the drive the data we want to write. Otherwise, just drive the value 32'b1. I'd expect this to work as a mux,
// where it either drive the MyData bus from the DataToWrite latch or from a fixed value of 32'b1.
assign MyData = (State == TRASHSTATE ? DataToWrite : 32'b1);
---


Can anyone add any clarity?

Thanks very much.

try "output [31:0] MyData;", which instead of "wire [31:0] MyData;".
Good luck!

I did try it, but as expected in/out statements are only allowed at the top. Compiler complained and said "expecting 'endmodule' found 'output'

module Data ( CLK, Data);
input Clk;
output [31:0] Data;
...

reg [31:0] DataToWrite;
...
assign Data = (State == TRASHSTATE ? DataToWrite : 32'b1);
endmoudle

/******************************************************************************/
module top_module(CLK, MyData);
input CLK;
ouput [31:0] MyData;

wire [31:0] rMyData;

Data rMyData
(
.CLK(CLK),
.Data(rMyData),
);

assign MyData=rMyData;

endmoudle