fpga4fun.com

Firstly I would like to say What a great site. I've learnt a hell of amount of infomation from here.

Anyway i have a question. I'm using Altera's Baseline in verilog to create a new board that I require. I have an address bus and data bus. I can't seem to get the databus to be bi-directional, I have 2 Config registeres that i would like to read and write to but i can only get the compiler to allow me to assign the databus to 1 of them.

Ps. Any chance of doing a USB project on a FPGA.
PPs, Some other infomation that maybe useful to put on the pages are configuration devices and alteratives and a description of the JTAG protocol. I found using a FTDI FT232M chip i could program an Altera via JTAG using it until i changed to a larger device and use a EEPROM.

Pliers.

As far as I know, to set data bus to outputs and write:

data_bus <= '11001011';

To set to inputs:

data_bus <= 'zzzzzzzz';

and read:

whatever <= data_bus;

Is this what you are trying?

I'm Trying this:

cut Down Example

module Bob(Clk,Data,SelectL,SelectH);
input Clk;
input SelectL,SelectH;
inout Data
reg [15:0] Count;

always @(posedge Clk) Count <= Count + 1;

assign Data = SelectL ? Count[7:0] : SelectH ? Count[15:8] : 8'bz;

endmodule

assign Data = SelectL ? Count[7:0] : SelectH ? Count[15:8] : 8'bz;

This says..

If SelectL = 1 then Data = Count[7:0]
If SelectL = 0 and SelectH = 1 then Data = Count[15:8]
If SelectL = 0 and SelectL = 0 then Data = 8'bz

Right?

yes.

No, I mean, is that what he wants?

..So what's the problem? What's the observed behaviour?

Doesn't look like a register read/write mechanism anyway..!

This is just a multiplexer, so that he can read a 16 bits value on a 8 bits bus.
Be careful as the counter might increment during the read.