fpga4fun.com

where FPGAs are fun!

Skip to content

Verification technique for VHDL designs

If you have an FPGA product to advertise (unrelated to fpga4fun), you can make a post here. This may be erased at any time.
Post a reply

Verification technique for VHDL designs

Postby sarathtm » Sat Jun 19, 2010 10:16 pm

Is there any verification technique which is very efficient and faster which can do the functional verification and makes designers work better?
sarathtm
 
Posts: 3
Joined: Sat Jun 19, 2010 10:00 pm
Top
Post a reply

Return to Advertisement