Clocking Xylo-EM

Saxo/-L & Xylo/-EM/-L/-LM boards

Clocking Xylo-EM

Postby dellaenterprises » Sat Jul 17, 2010 9:02 pm

I need to feed a 320MHz LVPECL clock into an FPGA for a design which then allows me to have a synchronous 4 bit counter following for my lower frequencies (like Flashy). Is the Xylo-EM board able to add an external LVPECL crystal oscillator somewhere on the board? (I've currently got a 7mm x 5mm SMT part).
Thanks,
Teddy
dellaenterprises
 
Posts: 13
Joined: Mon Jun 21, 2010 9:39 pm

Postby fpga4fun » Sun Jul 18, 2010 3:35 am

Xylo-EM can't take an LVPECL signal directly.
Also 320MHz is very fast, might be a problem with a regular LVCMOS signal too.
fpga4fun
Site Admin
 
Posts: 837
Joined: Thu Sep 18, 2003 6:47 am

Postby dellaenterprises » Sun Jul 18, 2010 4:55 pm

From Altera web site: "Cyclone II devices support
the LVPECL input standard at the clock input pins only", so I guess my question becomes, are the clock input pins brought out to pads on the Xylo-EM board. I could jumper the signals directly from a second board that holds the 320MHz xtal. LVCMOS will just not support above about 160MHz.
dellaenterprises
 
Posts: 13
Joined: Mon Jun 21, 2010 9:39 pm

Postby fpga4fun » Sun Jul 18, 2010 4:59 pm

Ok, I guess I was wrong.
Does Cyclone-II support LVPECL at 320MHz?
fpga4fun
Site Admin
 
Posts: 837
Joined: Thu Sep 18, 2003 6:47 am

Postby dellaenterprises » Sun Jul 18, 2010 5:56 pm

From Chapter 5 "DC Characteristics and Timing Specifications" of the Cyclone II data sheet, max input speed for LVPECL based clock is 402MHz.
dellaenterprises
 
Posts: 13
Joined: Mon Jun 21, 2010 9:39 pm

Postby fpga4fun » Sun Jul 18, 2010 10:12 pm

You can find the list of the pins available in chapter 39.3 of Xylo-EM's doc.
Pins 88, 89 and 93 on CONIO1 might be used as clocks.
fpga4fun
Site Admin
 
Posts: 837
Joined: Thu Sep 18, 2003 6:47 am

Postby dellaenterprises » Sun Jul 18, 2010 10:47 pm

That might work, though I'll have to reroute the Flashy to some alternate pins for 88,89. One last question I hope, from Altera:

"When Cyclone II dedicated clock input pins are configured for the LVDS or LVPECL I/O standard for input operations, the differential buffer is powered by VCCINT, not VCCIO"

On the Xylo-EM these are pins 50,62,124,131.
Are these pins tied to a supply, or not connected by any chance?

Thanks
Teddy
dellaenterprises
 
Posts: 13
Joined: Mon Jun 21, 2010 9:39 pm

Postby fpga4fun » Mon Jul 19, 2010 2:27 am

VCCINT are connected to 1.2V on Xylo-EM (which is required by the Cyclone-II family).
fpga4fun
Site Admin
 
Posts: 837
Joined: Thu Sep 18, 2003 6:47 am


Return to FX2 FPGA boards