fpga4fun.com

Hello,

Using the bidirectional USB verilog program as a starting point, I've modified it to send 512 bytes at a time up to the PC via the USB. Modifying the C program, I send 100 request to the FPGA to reply with the 512 bytes. The 512 bytes come quickly, but there is a long delay (0.5 milliseconds) between USB responses. Is there some way to have the FPGA send continuous USB blocks without this delay? I need to send up 400K bytes at at time.

Thanks,
fred

What happens if instead of making 100 requests of 512 bytes, you make one request of 51200 bytes?

I thought the FX2 chip was limited to the size of the FIFO, 512 bytes. Thus I was using BulkInPipe4 and only expecting to get 512 bytes per call. Is this incorrect?

Fred

The FX2 has a limited FIFO but the CyUSB driver supports bigger requests. I think the maximum allowed is 65535 bytes.
The advantage of a bigger request is the higher bandwidth. The drawback is that it returns only once all has been received/sent.

So do you need to do a PKTEND for each 512 byte transfer from the FX2 out to the PC or do you write data continuously (letting the FX2 decide when its buffer is full and transmit) and wait until the end of the big block and just do one on the last block?

Last block.

Does the FPGAconf.exe program set the AUTOINLEN value of the FX2 chip when it is first run? It seems like you'd have to know the AUTOINLEN value to know how to push large amounts of data out of the FX2 chip so that you know when you have to use the PKTEND on the final block.

Not sure about AUTOINLEN, but just assert PKTEND when you are done.