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I'm having trouble with the DAC control to the Flashy board. From what I can tell, the output from the fpga's DAC control pin goes directly to the DAC's clk input. This same signal is low pass filtered and connected to the DAC's data input, then LPF'd again and connected to the DAC's load input.

The problem I'm having is that whenever the data consists of a string of zeros, the 'load' line goes low before I'm done clocking the data into the DAC. This confuses the DAC and it's outputs jump around. Even the demo code that I have appears to do the same thing. Is there a way to keep the DAC's load line high until after I'm done clocking data in? I must be missing something.

Thanks.

Are you driving the DAC control line from an FPGA or CPU?

I'm driving it from the FPGA. I've got the Xylo-LM. I started with the FlashyMini example Verilog code and it looks to me like the problem exsists even there.

Thanks again.

Does FlashyDemo work?

I loaded in FlashyDemo. When I look at the DAC control lines with a scope I can still see the load line going low before all the bits are shifted out.

By sliding the V-position and V-range bars all the way to the right, I can see the DAC outputs jump around. However, only DACC and DACD are jumping around, which may also have been the case before (I've been playing with the pots and I don't remember). I have the single Flashy, not the double, so maybe the jumping has to do with that?

When I slide the V-position and V-range bars all the way to the left, all of the DAC outputs are stable.

Could be that your Flashy is defective.
Do the trace on the scope display work fine? Do they move when you move the sliders?

The trace on the scope display does work. It also does move a little with adjustment of the slider controls, not sure how much it's supposed to move. I'm trying to get some quantitative measurements on what my input numbers will translate to in my application.

Is the LOAD line (pin 8 on DAC) supposed to stay high the whole time data is being shifted out? The TLV5620 data sheet indicates that it should. But I don't see any way that you can keep it high if the the last few data bits are all zeros. Does yours stay high?

The sliders are limited for V-pos, but we are working to extend the range in the new Flashy revision (N).
I don't have details on the LOAD pin, sorry.