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Hello Everyone,

If this question is already answered, I apologize and ask that someone point me to the previous post.

I am working on a project to talk directly to my Saxo-L board. What I want to do is configure the FX2 directly from my app. Initialize the slave FIFO with 8 bit bus and configure the Flags, CLKOUT freq. and so on.

I either keep on overlooking this information in TRM or it is not there to begin with, what I need to know is what address or endpoint do I write the configuration information for the FX2.

Any help is greatly appreciated, thanks everyone.

Did you make any progress on this? Last night I looked at the pin mapping between the fx2 and the xilinx part, and it didn't look immediately obvious how the fx2 could config the xilinx.

Hi seattleEE,


I have since decided to put that project on the shelf, the board I am using has the Altera Cyclone. What I was trying to do was interface with a cmos image sensor, and I did not want to load firmware via eeprom, for the simple fact of development purposes. I had the idea of downloading the FX2 firmware from the PC app and after testing was complete finalize the design by using the eeprom firmware load option. I have seen it done with fX2pipe written by Wolfgang Wieser, and Jean does it with the supplied config applications.

When I wrote the previous post I was gathering information, the fx2 interface was only part of a larger project, as far as the pin mapping goes, it is supplied with the sample project files, Thanks for the interest, and if you have anything to add, please feel free, I am not above learning something new, Thanks again.

Thanks for the pointer on FX2Pipe. I wasn't aware of that.

Regarding the mappings...You tell the xilinx how you will configure it via the M[2..0] pins. However, each of those configs requires clock into or out of CCLK. What is confusing to me is that the FX2 clock goes into GCLK7. It might also go into CCLK on the PCB I haven't checked.

But, it would see to me the most straightforward way of config'ing the xilinx part would be slave parallel or serial slave mode. Slave parallel uses D[7:0] on xilinx, and those aren't connected to the FX2 that I can see. Serial slave uses DIN on the xilinx, and that also appears not to be connected.

Does anyone know how the FX2 is doing this?

What I need to do next is capture M[2..0] on the rising edge of INIT_B and then work backwards from there. I also need to check I have the right pin out...

Check to see if it's using the JTAG pins.

Doesn't look like it. JTAG on XC3S500E are pins 155, 157 adn 158. And those look to be NC

Hi, i'm new here but know a little about config a xilinx with the fx2.

Pins needed are usally...

FX2.........................FPGA
RDY0.......................BUSY
CTRL1......................R/W
IFCLK.......................GCLK0
CTRL0......................CS_B
PB0..........................D7
PB1..........................D6
PB2..........................D5
PB3..........................D4
PB4..........................D3
PB5..........................D2
PB6..........................D1
PB7..........................D0
PA1..........................DONE
PA2..........................INIT_B
PA3..........................PROG_B

If you need more help just ask.

I checked the Mode select pins and it was M2->0,M1->0,M0->1. This means that the FPGA is always configured in SPI serial mode. What doesnt make sense to me is how does the initial configuration takes place? In order for the FPGA to be loaded initially from FX2 via the GPIF interface, the FPGA's mode select pin needs to be set for the slave parallel mode, right??