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I hope some one can help me with this dilema...

I am using Xylo-EM (rev A) with Flashy-D (rev H).

I have read up the oscillator tutorial and about synchronizing different clock domains to try to and fix my problem to no avail.

Sorry for the long post but I seem not to be able to explain in short:

The Flashy-D ADC is at 100MHz and USB2 is at 48MHz. I am capturing at 100MHz samples and processing, which contains data at 4MHz. I think the USB2 is capable of streaming this 4MHz data to PC in real time, no? Problem is the data is in the 100MHz ADC clock domain - unrelated to the 48MHz USB2 clock domain.

I've tried using a FIFO to synchronize the clocks, but it doesn't work - it creates long delays (longer than 4MHz!) and plus it seems it does not allow simultaneous read/write. *Note, I have tried writing to FIFO until full and then send to USB2 - it works. But this is not real time - I will be missing some 4MHz data when I restart filling FIFO again (seems the synchronizer is the culprit here - very long delays).

I have a solution - it's to use the FPGA PLL1 to generate 48MHz * 2 = 96MHz and disable the 100MHz clock, then to use this instead.

Now my problem is there are 2 PLL outputs, pll_out_p (positive terminal, pin 31) and pll_out_n (negative terminal, pin 32). Does any one know how I can connect them to the Flashy D?

Yes, 4MHz real-time streaming should work. A FIFO should be fine (and probably the best solution). You can do simultaneous read/write using different clocks. No need for a PLL there. If you make the FIFO big enough, it can store data even if the PC stops pulling data (so that you don't miss data... unless the FIFO gets full because the PC got lazy too long).

You don't need to push the FX2 clock to 48MHz. Even 12MHz should work, since you send at 4MHz. If you use a PLL, you don't have to use the pll_out pins, you can use the PLL inside the FPGA. But I don't think you need a PLL.

Sorry to say, but I don't think it does do simultaneous read/write or something wrong with my code.

I have a sample program here that does simulataneous read/write. It is for the above mentioned hardware.

The process starts when a single byte is received from USB2.
The ADC 100MHz clock is divided by a counter by 32, so 100/32=3.125MHz. This is used to increment a counter of 0..255 repeatedly. At each increment it is written to a FIFO (1024 bytes deep). In parallel the USB2 clock reads from the FIFO and writes it to the USB2 for the PC.

My C program USB_test reads the data and checks if it's consecutive. It always finds offset 1024 byte is not consecutive - this means that it read after FIFO is full or the synchronizing code of FIFO is so slow! Either way it seems it's not doing simultaneous read/write!

The FIFO was created from the Mega Wizard with unrelated clocks, synchronizing handlers setting.

HTTP link:
http://www.cdtool.pwp.blueyonder.co.uk/USB_send_to_PC_with_myfifo1024_65024_async.zip

A few comments on your code:

1. Please do not post code that is part of the kit (it is copyrighted). You are welcome to post your own code of course.
2. What speed do you use for the FX2 bus? I recommend to get it working at 12MHz first (to avoid timing issues). In particular, I noticed that you drive many FX2 signals using combinatorial logic (Tpd is longer). If you can use registered outputs, that's better. At 12MHz, that wouldn't do a difference though.
3. I noticed that the signals FIFO_WR and rdreq are not consistent (my guess would be that you write to the FX2 FIFO at the same time you read from the FPGA FIFO).

These are quick comments... sorry I can't really go into your code.

Questions:

1. What version of .net are you using? I tried Visual C++ Express edition 2005 but it complains about "#include <windows.h>" missing.

2. There is an ugly bug in the file (I fixed it in the latest dev kit).
> assert(nBytes=buffersize); // make sure everything was sent
should be
> assert(nBytes==buffersize); // make sure everything was sent

>1. Please do not post code that is part of the kit (it is copyrighted). You
>are welcome to post your own code of course.
I am very sorry. I won't do it again. I've removed the file to that link.

>2. What speed do you use for the FX2 bus? I recommend to get it
>working at 12MHz first (to avoid timing issues). In particular, I noticed
>that you drive many FX2 signals using combinatorial logic (Tpd is
>longer). If you can use registered outputs, that's better. At 12MHz, that ?
>wouldn't do a difference though.
I've tried 24MHz and 48MHz. Ok, will try 12MHz.

>What version of .net are you using? I tried Visual C++ Express edition
>2005 but it complains about "#include <windows.h>" missing.
I'm using my work place MS Visual C++ 7 (2002).

windows.h is not part of Microsoft Visual C++ anymore, you need to download the Platform SDK if you want to compile old windows programs. You might need to set the paths manually too so it can find the files.

Thanks for the info - I'll try that. Looks like the latest is called Windows® Server 2003 R2 Platform SDK

Works!
I had to manually add the "include" and "lib" directories into the project setttings, as you mentioned...

I've made it work. You were right, FIFO does do simultaneous read/write. Now I'm off to rewrite the code from scratch and delete the previous code I was using.

Great!

Hi Truong,

Look like you can make USB work with Flash A/D board. Great !!!
I just have dragon board and Flash A/D board. I am try to make the FPGA code to got data from Flash and send to PC. Please share your FPGA and PC code, this may save me a lot of time. My board is different from yours but I can got some idea.

Thanks in advance.

Tran
email: tranvietnam@yahoo.com