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I like your idea of using a 500 byte FIFO buffer to build an oscilloscope. I have never used a FPGA and was wondering if a 500 byte FIFO buffer exists as an IC that I can buy. If not, how big of a buffer can be made with a Xylo, if all of the resources were devoted to the buffer? I plan on using the FLASHY along with a buffer controlled by an AVR. The AVR is too slow to take measurements in real time so I plan to make the flashy data go directly into the FPGA buffer when a trigger happens and then the AVR will take the data out of the buffer for displaying on the LCD. The AVR is much slower than the FLASHY but it can update the entire lcd fast enough.

The EP1C3 used by Xylo has 13 of these 512 bytes memories. You can stitch them together and use them as memory for a FIFO.

Why not just use 6500 bytes for the buffer? If each reading is oversampled and the range increased, the instrument could zoom in on the signal or move forward or backward unlike the limited way my school's bench scope does.

The cost of this project may get high. LCD, AVR, FPGA, FLASHY.

yes, up to 6500 bytes.
I kept my design with a 512 bytes buffer to keep it simple.

maybe it would be most cost effective to interface FLASHY directly to an SRAM chip and then use a microcontroller for the display. Can a Flashy connect to SRAM instead of an FPGA?

sure but you need logic to control the SRAM anyway... the FPGA is (in my opinion) the best way.

Sorry to bother you so much. How can an 8 bit wide buffer take in data at 100MHz, (in 10ns) when discrete ram isnt available in speeds that fast? Are your FPGAs faster than SRAM?

yes, the RAM in the FPGA go faster than 10ns. I got the FlashyD design to go to over 150MHz with Pluto-II. I fastest FPGA I've seen go to around 2ns (500MHz). That would very hard to do with discrete components!

Hi,

Sorry to revive this topic but first post and it seemed like it fitted in here rather than starting a new one.

I too am (attempting) to design my own digital oscilloscope and its seemed that progarmmable logic, be it CPLD or FPGA based was the only way to go. What confuses me is the SRAM implementation.

I understand the FIFO design, very handy, but I am not sure why dual port ram was needed. Was this simply to 'make things easier' as you had the resources available to you in the FPGA? If I was to make a cheapy osc, with a CPLD and an external SRAM chip, surely I could use the CPLD to write data from the ADC to the SRAM, and then read the SRAM to output the data.

Although I can read VHDL/verilog fairly well, I couldn't see that both writing AND reading to the RAM was occuring at the same time. So effictively a cycle would be (not code):

start
trigger ADC
write to ram
iinc ram until <=512.
reset ram address to 0
read ram, output data
inc ram until <=512.
goto start.

Of course dual-port ram or a FIFO would be needed in order to write/read at the same time. - Am I correct or am I totally out of my depth on this one? My life would be easier if I could just use simple SRAM rather than special memories.

Cheers,

Scott.