SEU mitigation in Virtex 5 FPGA

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SEU mitigation in Virtex 5 FPGA

Postby sumits » Sat May 15, 2010 6:17 pm

Hi All,

I was going through various Xilinx applications for SEU mitigation strategies and read about the partial reconfiguration feature. FPGAs can be configured in either Master or Slave mode. There are inbuilt features like CRC checks and ECC checks in Virtex 5 which actually check whether any SEU error has occurred into the configuration memory and tells the exact effected frame location.

My question is that whether there is any inbuilt feature in Xilinx Virtex 5 FPGA that can perform re-configuration (partial or complete) by itself.

Please let me know your views regarding the same.
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