4 bit binary multipication

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4 bit binary multipication

Postby sihab » Sat May 08, 2010 10:45 pm

Hi guys, can some one help me to solve my VHDL problem. Below i wrote the problem.

entity Multiplton_4Bit is
port(En: in BIT; Oprn1, Oprn2: in BitVect4; OutDta: out BitVect8; PSW: out BitVect6);
end Multiplton_4Bit;

such that if the enable bit (En) equals '1' then the operands (Oprn1), (Oprn2), which are 4- bit signed numbers, are multiplied to yield an 8-bit product (OutDta). The 6-bit (PSW) denotes the processor status word: bits 0, 1, 2, 3 represent the sign (S), zero(Z), carry-out (C), parity (P) bit respectively, and all other bits are zero to ‘0’ and reserved for future development. The latency for the device equals four-fold of the latency of an 4-bit full adder, and these values are provided in the package declaration design unit (provided).

C equals one if the carry-out bit of the arithmetic operation is 1, and zero otherwise; P equals one if the result has an even number (0, 2, 4, 6, ...) of 1’s, and zero otherwise; Z equals one if the result is all 0’s, and zero otherwise; S equals one if the most significant bit (MSB) of the result equals 1, and zero otherwise.
As an example, the setting En='1', Oprn1=“0111”, Oprn2=“0101” results in OutDta=“00100011”, PSW=“000000”.

Can some one help me to multiply this 4 bit binary number using 8 bit full adder, 8 bit rotate to the left and 4 bit multiplier. here is the package :

-- April 27, 2010

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

package HW2A_Pack is
constant FA_1BDly: TIME:= 5 ns; -- delay for 1-bit full adder
constant FA_8BDly: TIME:= 8 * FA_1BDly; -- delay for 8-bit full adder
constant RL_Dly: TIME:= 1 ns; -- delay for 1-bit rotation to left
constant MP_4BDly: TIME:= 4 * (FA_8BDly + RL_Dly); -- delay for 4-bit multiplication

subtype BitVect4 is BIT_VECTOR (3 downto 0);
subtype BitVect8 is BIT_VECTOR (7 downto 0);

component FullAdder_1Bit is
port(En, CIn, A, B: in BIT; COut, Sum: out BIT);
end component;

component FullAdder_8Bit is
port(En, CIn: in BIT; Num1, Num2: in BitVect8; COut: out BIT; Sum: out BitVect8);
end component;

component Multiplier_4Bit is
port(En: in BIT; Oprn1, Oprn2: in BitVect4; OutDta: out BitVect8);
end component;

component RotLft_1Bit is
port(En: in BIT; InNum: in BitVect8; COut: out BIT; OutNum: out BitVect8);
end component;

end HW2A_Pack; -- close HW2A_Pack

I need the Vhdl program and test bench
Posts: 1
Joined: Sat May 08, 2010 10:29 pm

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