Help on running clock generator

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Help on running clock generator

Postby yongkiat » Wed Apr 21, 2010 3:19 am

i need a code which allow the clock to run on its own. a basic and simple one will do. thanks
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Joined: Wed Apr 21, 2010 3:11 am

Postby Yassen » Wed Apr 21, 2010 6:53 am


Your question is not clear. As with most digital ICs the clock source is connected to a IC pin externally (the case with FPGAs) or is available internally (as in many CPUs). So you already have a clock.
* If you will use the clock for synthesis - in your circuit, then you can write (here in Verilog):
Code: Select all
always @(posedge clk)
        // your code here

which means: Everytime a positive edge of the clock signal 'clk' is detected - evaluate your code. The clock signals acts as an event and you should 'check' for this event to occur.
* If you want to generate a testbench, then you can write (Verilog again):
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always #1 clk = ~clk

This is actually a clock generator that cannot be synthesized but only simulated. It means: Always, at every 1-time-unit (this is #1), invert the clock signal 'clk' and assign it to itself - that is in fact to toggle the clock. The time unit can be specified using the 'timescale' directive that must be put at the very beginning of the testbench file.

Hope this helps.
And, please, do not repeat your question in more that one forum thread at a time ;-)

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Joined: Thu Jun 08, 2006 6:46 pm

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