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HI EVERYBODY,

I HAVE AN ENCODER SIGNAL OF 0.16 MICROMETER PER PULSE, AND I NEED TO TRANSLATE TO 1 MICROMETER PER PULSE. SINCE THE DIVISION IS NOT EXACT, MAYBE I CAN USE A FPGA TO DO THIS WORK? THE INCOMING SIGNAL (FROM ENCODER) IS A DOUBLE ENDED, QUADRATURE PHASE AB SIGNAL AND THE OUTGOING WILL BE THE SAME TYPE, BUT SINGLE ENDED TTL.

I'VE SEEN PLUTO BOARDS CAN DO THE FIRS PART OF THE WORK (DECODE A CUADRATURE ENCODER SIGNAL), BUT DUE I'M TOTALLY NEW ON FPGAS, I HAVE NO IDEA HOW TO GENERATE THE QUADRATURE SIGNALS ONCE "DIVIDED".

THANKS IN ADVANCE!!!!!!!

Hi botebotero,

It could be feasible but some information are missing to be able to study the problem.

Can you give a link on the encoder datasheet ?
What should be the accuracy?

Thoma

hi, Thoma.

the encoder is actually a interferometer system, but for simplicity, i told about a typical encoder, since it gives the same kind of signals. The interferometer system has a output board of type "EXCEL 1060a"; there is no information over w3, as far as I am aware, apart from a small product brochure at

http://www.excelprecision.com/splash/ex ... asheet.pdf
(page 4)

So I had to do some "reverse engineering" to use the card, but finally, it works. This card gives the result that you can view at:

http://www.metacafe.com/w/4476548

The signal you can view in the scope is a single ended, TTL AB phase cuadrature, about 10mhz. Originaly the board gives diferential outputs due the high frequency of the positioning signal, but i had take the signal before on the board, when already are TTL.

very very Thanks!!!

Hi botebotero,

I wrote a small VHDL description that permits to obtain the below result:



Do you think that this will solve your problem?

Thoma

OH, it looks really good. ¿how many time did you spent to obtain this result?

The division factor is ok as far i aware. I didn't analyze how is the behavior in case of direction changue on a normal encoder signal to compare against this one, but i'll do as soon i can.

The clk is internal or must i supply externally?

There is a inexpensive board called Pluto Do you think it fits?

thanks!!!
Mario

Hi Mario,

As I already had to solve a similar problem, the modification took two hours and the test bench around a half hour.

I updated the test bench and corrected the description (there was a small bug in some situations of direction change). I also add two counters to the test bench to simplify the checking of the divider behavioral.

It will fit in the Pluto board and if you take a look on the board, you will see a clock source. If you want an autonomous system, choose one with a boot PROM. I think that it will also fit in a CPLD as it take only 22 equations.

Thoma

hi Thoma,

So when yoy told about a bench, you mean this image were real hardware signals?

Certanly, this problem apears, on many situations when you deal with servo systems, since you must say to the servodriver how many pulses are needed for every motor revolution.

before that, i just assume there was any way to divide the feed pulses, but don't think about how. (but missed thinking this is no an exact division). Now i'ts a bit clear how do.

May be you can tell me what i need to get the system working.

By the way, i'm from Madrid, Spain, and live at Cordoba. and you?
Now, wuile write that, i'm listening a prodigy song at jango and enjoying a bits of chocolate (72%), nearly perfect.


Thaks!

Hi Mario,

The test bench is more an exerciser that simulate the environment under ModelSim. I write them in VHDL. Here below, you will find the one used to check the description.

Code: Select all

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY reencoder_tb IS
END reencoder_tb;

ARCHITECTURE behavior OF reencoder_tb IS

    component reencoder
    port(
         clr : IN  std_logic;
         clk : IN  std_logic;
         sclr : IN  std_logic;
         aIn : IN  std_logic;
         bIn : IN  std_logic;
         aOut : OUT  std_logic;
         bOut : OUT  std_logic
        );
    end component;
   
  component quad_decoder
  port ( a    : in    std_logic;
         b    : in    std_logic;
         clk  : in    std_logic;
         clr  : in    std_logic;
         sclr : in    std_logic;
         co   : out   std_logic;
         q    : out   std_logic_vector (31 downto 0));
  end component;

   signal clr : std_logic := '1';
   signal clk : std_logic := '0';
   signal sclr : std_logic := '0';
   signal aIn : std_logic := '0';
   signal bIn : std_logic := '0';

   signal aOut : std_logic;
   signal bOut : std_logic;
   signal position0 : std_logic_vector(31 downto 0);
   signal position1 : std_logic_vector(31 downto 0);

BEGIN

   uut: reencoder PORT MAP (
          clr => clr,
          clk => clk,
          sclr => sclr,
          aIn => aIn,
          bIn => bIn,
          aOut => aOut,
          bOut => bOut
        );

  qd0 : quad_decoder port map (
         aIn,
         bIn,
         clk,
         clr,
         sclr,
         open,
         position0);

  qd1 : quad_decoder port map (
         aOut,
         bOut,
         clk,
         clr,
         sclr,
         open,
         position1);

   process
   begin
      clk <= '0';
      wait for 20 ns;
      clk <= '1';
      wait for 20 ns;
   end process;

   process
   begin      
      -- hold reset state for 1.01 us.
      wait for 1.010 us;
      clr <= '0';

      for index in 0 to 99 loop
        aIn <= '1';
        wait for 100 ns;
        bIn <= '1';
        wait for 100 ns;
        aIn <= '0';
        wait for 100 ns;
        bIn <= '0';
        wait for 100 ns;
      end loop;

      for index in 0 to 99 loop
        bIn <= '1';
        wait for 100 ns;
        aIn <= '1';
        wait for 100 ns;
        bIn <= '0';
        wait for 100 ns;
        aIn <= '0';
        wait for 100 ns;
      end loop;

      sclr <= '1';
      wait for 100 ns;
     
      sclr <= '0';
      wait for 100 ns;

      for index in 0 to 199 loop
        aIn <= '1';
        wait for 100 ns;
        bIn <= '1';
        wait for 100 ns;
        aIn <= '0';
        wait for 100 ns;
        bIn <= '0';
        wait for 100 ns;
      end loop;

      wait for 1600 ns;

      for index in 0 to 4 loop
        bIn <= '1';
        wait for 800 ns;
        aIn <= '1';
        wait for 800 ns;
        bIn <= '0';
        wait for 800 ns;
        aIn <= '0';
        wait for 800 ns;
      end loop;

      wait for 2400 ns;

      for index in 10 to 14 loop
        aIn <= '1';
        wait for 400 ns;
        bIn <= '1';
        wait for 400 ns;
        aIn <= '0';
        wait for 400 ns;
        bIn <= '0';
        wait for 400 ns;
      end loop;

      wait for 3200 ns;

      for index in 0 to 9 loop
        aIn <= '1';
        wait for 400 ns;
        bIn <= '1';
        wait for 400 ns;
        aIn <= '0';
        wait for 400 ns;
        bIn <= '0';
        wait for 400 ns;
      end loop;

      wait for 1600 ns;

      for index in 0 to 9 loop
        bIn <= '1';
        wait for 800 ns;
        aIn <= '1';
        wait for 800 ns;
        bIn <= '0';
        wait for 800 ns;
        aIn <= '0';
        wait for 800 ns;
      end loop;

      wait for 2400 ns;

      for index in 10 to 14 loop
        bIn <= '1';
        wait for 800 ns;
        aIn <= '1';
        wait for 800 ns;
        bIn <= '0';
        wait for 800 ns;
        aIn <= '0';
        wait for 800 ns;
      end loop;

      wait for 1600 ns;

      for index in 10 to 14 loop
        aIn <= '1';
        wait for 800 ns;
        bIn <= '1';
        wait for 800 ns;
        aIn <= '0';
        wait for 800 ns;
        bIn <= '0';
        wait for 800 ns;
      end loop;

      wait;
   end process;

END;


quad_decoder is used to extract the pulse count.

My approach for this problem is:
- decode the quadrature signal to extract direction and progression,
- use a modulo 25 counter with an increment of 4: underflow and overflow are used to control a finite state machine and
- use a finite state machine to rebuild a down sampled quadrature signal.

I can provide some help or the complete description.

I am living in France near Paris.
Currently, I work for an automation company. And I work also as freelance.

Thoma

ok Thoma,

Here is my e-mail,

ar_mario_rl@yahoo.es

if you send me a simple email, i'll ask you about the correct steps.

If you need help on PLC programming some day please tell me.

MERCI.

ok Thoma,
I like to hear it's a simple problem to solve. May be in the future we can work together (with our respective professional hats on).

I said that because it would be pretty to develop a board capable to decode the signals direct from the interferometer optics, as my 1060a board from excel.

So what board do you recommend to use? ideally it could work without host hardware. The signals from te interferometer can reach up to 3-4mhz and are double ended. But the outcoming from our pretty electronics would be single ended.

THANKS!!

Hi Mario,

In case, you want a dedicated board, here are my assumptions:
- differential signal are 5V
- output are also 5V
- power supply will be 5V (no on board regulator)



The CPLD will regenerate the quadrature signal with a different factor (0,16µm/pulse down to 1µm/pulse).

Could you confirm this items?
Have you others requirements?
On your interferometer, did you have a reference signal to clear the position counter?
Will you describe the hardware with VHDL or verilog?

Concerning a none dedicated board, you must consider the fact that a low cost board do not have differential receiver and you must add a dual one.

The Pluto board have no boot PROM. The Pluto-II board should be suitable if you add a differential receiver.

Thoma

hi thoma,

Could you confirm this items? ->YES

Have you others requirements? ->NO

On your interferometer, did you have a reference signal to clear the position counter? ->NO, ACTUALLY THIS IS ANOTHER PROBLEM TO SOLVE, ENCODERS HAVE ZERO PULSE OR REFERENCE MARKS IF LINEAR, BUT INTERFEROMETER DON'T. I THOUGT SEVERAL TIMES ABOUT, AND I THINK THE ONLY WAY IS TO USE ANOTHER SMALL ENCODER, BUT ANYWAY IT WILL BE EXTERNAL ARRANGEMENT TO THE FPGA BOARD.

Will you describe the hardware with VHDL or verilog?->¿¿¿???

Concerning a none dedicated board, you must consider the fact that a low cost board do not have differential receiver and you must add a dual one.->YES, IF YOU KNOW ANOTHER BOARD WITH BUILT IN DIFF INPUTS YOU CAN TELL ME, OR I CAN MODIFY THE OUTPUT ELECTRONICS OF THE 1060A BOARD; I HAVE WATCHED SOME BOARDS FROM MESA ELECTRONICS THAT MAY BE SITUABLE, BUT I'M NOT SURE SINCE I DONT NOW HOW TO SELECT A FPGA SOLUTION.

The Pluto board have no boot PROM. The Pluto-II board should be suitable if you add a differential receiver. -> OH, IT'S NOT A PROBLEM. ALSO I CAN CATH THE POSITION SIGNAL IN MY 1060A BOARD WHEN ALREADY ARE TTL (5V) SINGLE ENDED. BY THE WAY, ¿WHAT IS A BOOT PROM? (¿FOR MANAGING THE BOARD FROM EXTERNAL HOST HW, LIKE IN A TYPICAL MICROPROCESSOR BOARD?)


HAVE A NICE DAY !!

Hi Mario,

What I call describe the hardware concerns the FPGA behavior?

The boot PROM permits to configure the FPGA at power up time. This is required as SRAM FPGA must be set up each time the power was down.

If you can provide single-ended quadrature signal then Pluto II could match your requirements.
As clamp diode are present in the EP1C3, the level could be adapt with a simple resistor. And single-ended outputs will be LVTTL (3.3V) signal.

I think the next step is to gather all collected informations.

Thoma

hi Thoma,

How can i describe the hardware, i have no idea about VHDL or VERILOG.

I thougt the cronograph above was generated by a simulation of a fpga program created in some languaje. is vhdl that languaje?

may be i need to work more on my fpga knowledge before going ahead

Thanks Thoma!!!