fpga4fun.com

I'm trying for like 4 days to make Altera DE2 Cyclone FPGA board to "play" any kind of sound but it is killing me!

I made the VHDL code setting an input being clock and an output being "speaker". I basically use process on the clock and make a counter for a 16 bit vector, which will only be incremented on rising edges for the clock. Then I want speaker to send out counter(15) ...

I tried following the music box from the website but it's not working, either in VHDL or Verilog... also the waveform comes out wrong...
Someone can help me??

Post your VHDL / Verilog source. How is the waveform wrong?

code is

entity midiplayer is
port ( clk : in STD_LOGIC ;
speaker: out STD_LOGIC);
end midiplayer

architecture player of midiplayer is

begin
process(clk)
begin
variable counter:STD_LOGIC_VECTOR(15 downto 0);
if (clk'event and clk='1') then
counter := counter + 1;
end if;
speaker <= counter(15);
end process;
end player

Since I left the code at my university, can't really recall EXACTLY how it was, but it's 95% look aliked to this(typed out of head)

The waveform for this should be 1 when it reaches the rising edge for the 15th bit, but it all stays 0.

You're assigning the MSB of counter to the speaker signal in a process that doesn't have counter in its sensitivity list (your synthesis software probably gave a warning about this). I usually play it safe and do all the assignments outside the processes, because I always forget to update the sensitivity list.

Well, I'm using Quartus II and the FPGA board is Altera DE2 Cyclone II.
So I should put the variable for the counter outside the process(clk)?
Also, how do I say the clk input is 25 MHz and all of that? I'm trying to make the "MusicBox" out of this website but it's not working at all :/

hello.I have the same problem with the DE2 board. Have you find the code?
please help meeeeeeeeeeeeeeeee. I have begun with i2c but it doesn't functionned