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In the PCI, you state that there is now way to constrainst hold time. Actually there is !
I found out recently that you can specify the "data valid window".

TIMEGRP "pci_bussed" OFFSET = IN 7 ns VALID 7 ns BEFORE "pci_clk" HIGH ;


So :

Code: Select all

    ____                _______
Clk     \              /
         \____________/
    _______  ______________  _______
DO         \/              \/
    _______/\______________/\_______
   
           |----Tsu----|
           |---Valid-------|


Thus, having Tsu = Valid = 7ns gives a 0ns hold time constraint.


Also, for the final design, a multi pass place & route can help.

Thanks, looks good - I'll have to update that once I revisit PCI!