fpga4fun.com

PCI specifies timing are:
- Tsu/Th=7ns/0n
- Tco=11ns

In my design I obtain some time-path with Tsu greather than 7ns ( 10 ns) - e.g. from pci_data to pci_clk.
What happens??? What it will work wrong???
I made all the settings for improve Tsu (I use QuartusII with an acex1k).

Lucas.

So to get faster timing, you can try to:
1. change your HDL code
2. use a faster FPGA
3. play with Quartus settings