PCI Timings

PCI Timings

Postby 246tNt » Sat Jul 10, 2004 6:32 pm

Hi

I'm trying to understand the PCI specifications, and there are some timings specs I don't understand.

They say that :

* For output:
t_val is CLK to output valid : min 2ns max 11ns

* For input:
t_su is Setup time beforce CLK : min 7ns
t_h is Hold time after CLK : min 0ns

* At 33Mhz, clk period is 30ns


What is an input for one chip of the bus is an output for another one.
So : Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns.
Why max 11ns ? Since setup time is min 7ns ...
Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle.



Sylvain Munaut
246tNt
 
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Postby fpga4fun » Sat Jul 31, 2004 5:13 pm

A few answers:

"Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle."
YES

"Why max 11ns ? Since setup time is min 7ns ..."
Output MAX 11ns means an output signal needs to be valid at most 11ns after the clock arrives. Then it has 12ns to go through the bus wires, to arrive at least 7ns before the next clock cycle at the destination. 11+12+7=30=one clock period.
fpga4fun
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