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Is the code for the ethernet UDP for a FPGA also usable for a CPLD? Or what would I have to modify to make it work?

It would work. But the code is kind of big for a CPLD, it's going to require an expensive CPLD. Also right now, I use a internal RAM to store the packets, so it would require an external RAM for a CPLD (I don't think you can find a CPLD with an internal RAM).

I tried it with 288 macrocell xilinx cpld. Practically no changes from the original code, and it worked.