Send Packet Difficulties

Send Packet Difficulties

Postby Jeison » Wed Nov 30, 2005 7:17 pm

I compiled the code shown in http://www.fpga4fun.com/10BASE-T0.html but it doesn't worked. After I assembled the hardware to network connection throught a transformer (20F001N), I programmed that compilation to the UP1 Altera Development Board using EPF10K20RC240-4. In order to verify the operation of that code, some tries were made.
In first time I put an internal clock (25,175MHz) but it doesn´t worked.
After I put an external 20MHz clock but also doesn't worked.
Finally I put an external 40MHz clock but also doesn"t worked.

So I am thinking that the problem is the FPGA device once the device used in that recipe is a ACEX rather than FLEX 10K.

Can it is possible?
Thank you.
Jeison
 
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Postby fpga4fun » Thu Dec 01, 2005 4:47 am

The EPF10K20RC240 should work.
The clock needs to be 20MHz (or 40MHz if you divide it by 2 in the FPGA). 25.175MHz will not work.

Check:
1. that your PC doesn't have a firewall enabled.
2. with an oscilloscope that you are getting a signal on the output pins.
3. the values that you are putting in the HDL code (IP...).
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It does't operate yet...

Postby Jeison » Thu Dec 01, 2005 10:39 am

I tried that ckecks that you sad, but it doesn't operate yet. However some things I observed. First: Althought I used a rigth clock of 20MHz, I noticed in Osciloscope attached to Ethernet_TDp and Ethernet_TDm that the signal shows every second, but the sinusoidal signal that apper has 5MHz. Second: I made compilations in both Max+plus II 10.2 Baseline and in Quartus II 5.0 Web, in the last one some warning messages are shown like truncating some values.

I am thinking that the problem can be the hardware that I connect the FPGA Ethernet_TDp and Ethernet_TDm pins. Do you have any solution to the interfacing to the ethernet cable.

Thanks.

Jeison
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Postby fpga4fun » Thu Dec 01, 2005 5:47 pm

Yes, the design sends an Ethernet packet every second. If you attach an Ethernet hub/switch to the cable, the LED should blink at the same rate.

The output is not a periodic signal, so it's hard to measure. Use your 20MHz oscillator with the design http://www.fpga4fun.com/10BASE-T0.html and you should be fine.

Also make sure you use the right pairs (pins 1/2 or pins 3/6 in the cable, as mentioned in the webpage).

The warnings are of no consequence.
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Now evething is right!

Postby Jeison » Thu Dec 01, 2005 8:49 pm

Thanks for the tips. Now everything are OK!
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Other tests

Postby Jeison » Fri Dec 02, 2005 10:00 am

Althought the system are operating, I noticed that when I did the connection using a crossed cable (same PC), the operation is OK, but if I use a network connection (throught Hub´s and switches using a straight cable) it doesn't operate. Why?
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Postby fpga4fun » Fri Dec 02, 2005 5:56 pm

1. verify your cable connection (with a scope, check that the signal comes on the right pins of the cable).
2. try different ports on different hubs/switches
3. ... don't know, should work!
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Postby raalst » Sat Dec 03, 2005 12:58 pm

beware of port 0 and port [max] on a hub or switch, as they might have a cross built in, or even speak some inter-hub protocol.

so indeed, try a few ports. in general, you do the right thing.

also some switches can be configured quite a bit, checking e.g.
MAC adresses. however, in that case your hub/switch would be
expensive, not normal home equipment.

good luck,
Ronald
Regards,
Ronald van Aalst
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Re: Send Packet Difficulties

Postby a.singh » Wed Apr 21, 2010 8:49 am

Jeison wrote:I compiled the code shown in http://www.fpga4fun.com/10BASE-T0.html but it doesn't worked. After I assembled the hardware to network connection throught a transformer (20F001N), I programmed that compilation to the UP1 Altera Development Board using EPF10K20RC240-4. In order to verify the operation of that code, some tries were made.
In first time I put an internal clock (25,175MHz) but it doesn´t worked.
After I put an external 20MHz clock but also doesn't worked.
Finally I put an external 40MHz clock but also doesn"t worked.

So I am thinking that the problem is the FPGA device once the device used in that recipe is a ACEX rather than FLEX 10K.

Can it is possible?
Thank you.

Hi Jeison, Please can u tell me clearly why this transformer 20F001N is employed. I have compiled my code in Spartan3, and LVDS as output and directly connected to RJ45 female connector. it is not working. please help me. :cry:
Abhishek
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