What of Actel Make

What of Actel Make

Postby xfpga » Mon Nov 14, 2005 2:18 pm

Hi,

I'm a newbie in this FPGA business. I found your work interesting cos i'm developing a virtual instrument which must be accessible by several users via a network.

I'm used to VHDL than verilog, could u help with any verilog 2 vhdl converter? the reverse is available though. I'm also using an ACTEL evaluation board for my work.

How easy will it be if i want to transmit other data from pc to FPGA and vice versa?

Thanks!
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Postby fpga4fun » Tue Nov 15, 2005 1:46 am

Ethernet 10BASE-T is pretty easy, I've successfully implemented UDP/PHY in the FPGA, see Xylo and Dragon boards. I've not tried 100BASE-T yet. I don't use VHDL or Actel, can't help there.
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Clock

Postby xfpga » Wed Nov 16, 2005 2:59 pm

Hi,

I implemented the 10BaseT on an ACTEL FPGA, I however did not get any results. the oscillator on the board is 40MHz. Will this work or i have to split the clock? Can U help me by convert the code to VHDL?

i don't know if i have to perform some other connection on the end that connects to the board, i just picked out the corresponding color codes and connected them to the boards I/Os, leaving the others.

Thanks!
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Splitting Clock

Postby xfpga » Mon Dec 12, 2005 2:10 pm

Hi,

Could U possibiliy show how i can plit a 40MHz clock into 2 on an FPGA using Verilog, if your design tools does not allow you to do that unless in the source file.

Thanks
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Postby fpga4fun » Mon Dec 12, 2005 5:08 pm

It's easy to do in the source file, use a flip-flop as a divide by 2.

reg clk20;
always @(posedge clk40) clk20<=~clk20;
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How easy

Postby xfpga » Tue Dec 13, 2005 1:24 pm

Hi, i extracted this code and wanted to simulate that only to observe how the cycle will be halfed. However i get 'X' as my output throughout.

How will this code change the existing one? Is the module declaration now going to have a port clk40 instead of 20 and all the others sourcing from reg clk20?

reg clk20;
always @(posedge clk40) clk20<=~clk20;

Thanks
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Postby fpga4fun » Tue Dec 13, 2005 5:11 pm

An FPGA is happy with this code as it initializes all flops to "0" at configuration time.
In a simulator, you have to initialize the clk20 to 0. Otherwise the simulator says he doesn't know the initial value, and put an "X" (=unknown) in there. Try an initial statement in Verilog.
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clock speed

Postby sarah_s » Sat Mar 29, 2008 4:47 am

Hi,

I am also trying to run this on a Actel board. The fpga is connected to the router, and I see the lights on the router go on/off. Looks like the fpga is sending data. But I don't see any information on the UDPreciever program on my PC. The fpga is running at 40Mhz. Is this the problem?

Regards,
Sarah
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Postby sarah_s » Sat Mar 29, 2008 5:31 pm

Guess it was the clock. It's working now at 20Mhz :)
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Postby sarah_s » Sat Mar 29, 2008 6:13 pm

How do I recieve 'useful' information from other FPGA pins? For example, I wanted to see the clock output?

Also, is UDP reciever implementation on the fpga also covered in that tutorial? I can read/write to the PC ethernet port using matlab/simulink.

Thanks for the support.
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