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I am having trouble with the first section of the sending. I am using the pluto board with quartus II 4.2. What I am am getting is it will clock in the first data into the pkt_data, but after this no more data is shidted in. I tried to look at the counter register and got the message Warning: Compiler packed, optimized or synthesized away node "counter[x]" for each bit in the register, Ignored vector source file node. I then looked at the qo line and it when high, but the never changed. The qoe line went high for a few clock and then went low the remaining time. Also the LinkPulseCount was synthesized out. Any Ideas on how I can make it so these lines will not be optimized out or how I might be able to get this to compile and simulate properly????

Are you using the code as shown here?
http://www.fpga4fun.com/10BASE-T0.html

I just compiled with Quartus II 4.2 and I don't get the warning you mention.

fpga4fun wrote:Are you using the code as shown here?
http://www.fpga4fun.com/10BASE-T0.html

I just compiled with Quartus II 4.2 and I don't get the warning you mention.

Are you able to recieve the packets according to the code mentioned in above link? I have compiled it in Spartan3 but unable to recieve. please help me. I have changed the IP address and MAC address as said. I think no more to do. May be i have not converted the voltage standard from LVDS to ethernet, due to which it was unable to detect. I don't know how to do this conversion, please help me.