## CRC32

### CRC32

hi everyone,

I have some problemes with the CRC32 calculation. when i use the EthernetUDP software from the project 10BASE-T FPGA interface, to generate 18 Payload length Data, the calculated checksum is "B3 31 88 1B", that is correct. but when i use a online CRC calculator like this one: http://www.zorc.breitbandkatze.de/crc.html, the result is diferent for exemple:
"0010A47BEA8000123456789008004500002EB3FE000080110540C0A8002CC0A8000404000400001A2DE8000102030405060708090A0B0C0D0E0F1011"(from Ethernet destination address to payload), the CRC is: "D3 75 89 78" why?

And what about the result of the CRC of the project 10BASE-T FPGA interface?

Dany

Posts: 1
Joined: Thu Apr 16, 2009 6:52 am

I've been searching for the answer to this all day, I found this but have yet to understand it!

A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to generate a CRC value
for the FCS field. The frame check sequence (FCS) field contains a 4-octet (32-bit) cyclic redundancy
check (CRC) value. This value is computed as a function of the contents of the source address, destination
address, length, LLC data and pad (that is, all field except the preamble, SFD, FCS, and extension). The
encoding is defined by the following generating polynomial.
G(x) = x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
Mathematically, the CRC value corresponding to a given frame is defined by the following procedure:
a) The first 32 bits of the frame are complemented.
b) The bits of the frame are then considered to be the coefficients of a polynomial M(x) of degree n-1,
where n is the number of bits in the frame. (The first bit of the Destination Address field corresponds to the
x ^(n-1) term and the last bit of the data field corresponds to the x 0 term.)
c) M(x) is multiplied by x^32 and divided by G(x), producing a remainder R(x) of degree 31.
d) The coefficients of R(x) are considered to be a 32-bit sequence.
e) The bit sequence is complemented and the result is the CRC.
The 32 bits of the CRC value are placed in the frame check sequence field so that the x^ 31 term is the leftmost
bit of the first octet, and the x^0 term is the right most bit of the last octet. (The bits of the CRC are
thus transmitted in the order x^31 , x^30 ,.., x^1 , x^0 .).
weird_dave

Posts: 6
Joined: Wed Jan 13, 2010 10:58 am

a) How do you complement the first 32 bits? I don't understand what this means.

b) Fine with that.

c) OK, that's easy enough.

d) OK

e) What's this complemented thing again?

I don't entirely understand the bit at the end either, are the bits of the result in the correct order or reversed?
weird_dave

Posts: 6
Joined: Wed Jan 13, 2010 10:58 am

weird_dave

Posts: 6
Joined: Wed Jan 13, 2010 10:58 am