I have found very interesting the informations on this web site.
I'm trying to develop an application with ethernet PHY and following the instruction , I have written a VHDL code;
now, I try to implement on my FPGA but I cannot receive anything on my PC.
I can post my VHDL code.
Can anyone help me?
or I'm interested also in use your code "as it is", could I generate a NGC module and integrate it as black box on my Starter Kit?
- Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ethernetSnd2 is
port (
clk50: in STD_LOGIC; -- 50 Mhz clock
rst: in STD_LOGIC; -- asynchronous active high reset
btn: in STD_LOGIC; -- send a new frame signal
TX_CLK: in STD_LOGIC; -- transmit clock from the PHY
TX_EN: out STD_LOGIC; -- transmit enable line to the PHY
TX_DATA: out STD_LOGIC_VECTOR (3 downto 0) := (others=> '0'); -- transmit data line to the PHY
led : out STD_LOGIC_VECTOR(7 downto 0) -- byte written on phy interface
);
end ethernetSnd2;
architecture Behavioral of ethernetSnd2 is
constant destinationMAC: STD_LOGIC_VECTOR (47 downto 0) := x"001D095214EE"; -- target MAC of the frame
signal counter : integer range 0 to 127 :=0;
type mem_array is array(0 to 78) of std_logic_vector(0 to 7);
signal mem: mem_array;
signal memLATCH : std_logic_vector(7 downto 0) := x"00";
type state_type is (IDLE,S0, S1,SendN1,WaitCLK0,SendN2,WaitCLK1,UpdateCOUNTER);
signal next_state, state: state_type;
begin
mem(0 ) <= x"55";
mem(1 ) <= x"55";
mem(2 ) <= x"55";
mem(3 ) <= x"55";
mem(4 ) <= x"55";
mem(5 ) <= x"55";
mem(6 ) <= x"55";
mem(7 ) <= x"D5";
mem(8 ) <= x"00";
mem(9 ) <= x"1D";
mem(10) <= x"09";
mem(11) <= x"52";
mem(12) <= x"14";
mem(13) <= x"EE";
mem(14) <= x"00";
mem(15) <= x"12";
mem(16) <= x"34";
mem(17) <= x"56";
mem(18) <= x"78";
mem(19) <= x"90";
mem(20) <= x"08";
mem(21) <= x"00";
mem(22) <= x"45";
mem(23) <= x"00";
mem(24) <= x"00";
mem(25) <= x"2E";
mem(26) <= x"B3";
mem(27) <= x"FE";
mem(28) <= x"00";
mem(29) <= x"00";
mem(30) <= x"80";
mem(31) <= x"11"; -- 11 = UDP
mem(32) <= x"05";
mem(33) <= x"40";
mem(34) <= x"C0";
mem(35) <= x"A8";
mem(36) <= x"00";
mem(37) <= x"2C";
mem(38) <= x"C0";
mem(39) <= x"A8";
mem(40) <= x"00";
mem(41) <= x"04";
mem(42) <= x"04";
mem(43) <= x"00";
mem(44) <= x"04";
mem(45) <= x"00";
mem(46) <= x"00";
mem(47) <= x"1A";
mem(48) <= x"2D";
mem(49) <= x"E8";
mem(50) <= x"00";
mem(51) <= x"01";
mem(52) <= x"02";
mem(53) <= x"03";
mem(54) <= x"04";
mem(55) <= x"05";
mem(56) <= x"06";
mem(57) <= x"07";
mem(58) <= x"08";
mem(59) <= x"09";
mem(60) <= x"0A";
mem(61) <= x"0B";
mem(62) <= x"0C";
mem(63) <= x"0D";
mem(64) <= x"0E";
mem(65) <= x"0F";
mem(66) <= x"10";
mem(67) <= x"11";
process(btn,state,TX_CLK)
begin
case state is
when IDLE =>
counter <= 0;
if btn = '1' then
next_state <= S0;
else
next_state <= IDLE;
end if;
when S0 =>
if counter = 70 then
next_state <= S1;
else
if TX_CLK = '1' then
memLATCH <=mem(counter);
next_state <= SendN1;
else
next_state <= S0;
end if;
end if;
when SendN1 =>
if TX_CLK = '0' then
next_state <= WaitCLK0; -- I wait for TX_CLK goes high
else
next_state <= SendN1;
end if;
when WaitCLK0 =>
if TX_CLK = '1' then
memLATCH <=mem(counter);
next_state <= SendN2; -- I wait for TX_CLK goes low
else
next_state <= WaitCLK0;
end if;
when SendN2 =>
if TX_CLK = '0' then
counter <= counter +1;
next_state <= S0; -- I wait for TX_CLK goes high
else
next_state <= SendN2;
end if;
when S1 =>
counter <= 0;
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process;
-- cocurrent process#2: state assignement
state_reg: process(clk50,rst)
begin
if rst = '1' then
state <= IDLE;
elsif (clk50'event and clk50='1') then
state <= next_state;
end if;
end process;
-- cocurrent process#3: combinational logic
comb_logic: process(clk50)
begin
if clk50'event and clk50 ='1' then
case state is
when IDLE =>
TX_EN <= '0';
led <=x"00";
TX_DATA <= x"0";
when S0 =>
TX_EN <= '1';
led <=x"FF";
TX_DATA <= memLATCH(3 downto 0);
when SendN1 =>
when WaitCLK0 =>
TX_DATA <= memLATCH(7 downto 4);
when SendN2 =>
when S1 =>
TX_DATA <= x"0";
TX_EN <= '0';
led <=x"55";
when others =>
TX_EN <= '0';
led <=x"88";
end case;
end if;
end process;
end Behavioral;